SHA1 Instruction Set for 128-bit Data Path Processing
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Solution Overview
Problem
Conventional software solutions for SHA1 secure hashing algorithms are inefficient due to reliance on standard 32-bit instructions and register/memory storage, requiring multiple cycles to perform operations like round calculations, rotations, and XORs, even with multiple execution unit processors.
Innovation Solution
A new instruction set architecture (ISA) utilizing 128-bit SIMD registers is introduced to optimize SHA1 hash round calculations, enabling four rounds of SHA1 operations per instruction with a 3-cycle pipeline latency, significantly reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional software solutions use standard 32-bit instructions and register/memory storage for SHA1 operations, then the implementation is compatible with existing processors, but the processing speed is slow requiring multiple cycles per operation
Solution Approach 1:
The patent changes the word size parameter from 32-bit to 64-bit operations. By using 64-bit registers and performing operations on 64-bit words, the processor can complete SHA1 round calculations in fewer cycles. The message schedule is reorganized into 64-bit words where each word contains multiple 32-bit message inputs, allowing parallel processing and reducing the total number of operations required.
Solution Approach 2:
The patent introduces a new dimension of parallelism by processing multiple message inputs simultaneously within 64-bit registers. Instead of sequential 32-bit operations, the system processes four 32-bit message inputs in parallel within a single 64-bit word, effectively adding a parallel processing dimension that accelerates SHA1 computation without requiring additional processor cores.
2Productivity
If multiple execution unit processors are used for SHA1 operations, then processing capacity increases, but the complexity of coordinating multiple units and the overhead increases
Solution Approach 1:
The patent makes existing processor execution units multi-functional by designing them to handle both general-purpose 64-bit operations and SHA1-specific operations. The same execution units that perform regular arithmetic and logical operations are also configured to execute SHA1 round functions, eliminating the need for dedicated SHA1 hardware while achieving accelerated performance through efficient utilization of existing resources.
Solution Approach 2:
The patent segments the SHA1 computation into independent 64-bit word operations that can be executed in parallel. By organizing the message schedule and round functions to operate on discrete 64-bit words, the system enables parallel execution across multiple processing units without requiring complex coordination, as each word can be processed independently through the same instruction stream.
3Loss of time
If 32-bit instructions are used for each SHA1 operation, then the instruction set remains simple and easy to implement, but the number of instructions required increases leading to more cycles per hash
Solution Approach 1:
The patent merges multiple 32-bit operations into single 64-bit instructions. By combining four 32-bit message inputs into one 64-bit word and performing SHA1 round calculations on the entire 64-bit word, the system reduces the number of separate instructions required. This merging approach maintains implementation simplicity by using standard processor instruction formats while dramatically reducing the total instruction count and execution time.
Data Source
AI summary
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.