SHA-1 Processing Architecture Using Wide Registers and SIMD
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Solution Overview
Problem
Conventional software solutions for SHA-1 secure hashing algorithms are inefficient due to their reliance on standard 32-bit instructions and register/memory storage, requiring multiple cycles to perform operations like round calculations, rotates, and XORs, even with multiple execution unit processors.
Innovation Solution
A new instruction set architecture (ISA) is introduced that allows multiple SHA-1 operations to be performed in parallel using registers with at least 160 bits for state variables and 128 bits for message inputs, enabling a single instruction multiple data (SIMD) approach to optimize the SHA-1 computation by reducing the time required for round calculations and message scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional software solutions use standard 32-bit instructions and register/memory storage, then the implementation is compatible with existing processors, but the processing speed and efficiency of SHA-1 algorithm are insufficient
Solution Approach 1:
The patent changes the parameter of register width from standard 32-bit to wider registers (160 bits for state variables, 128 bits for message inputs), enabling parallel processing of multiple SHA-1 operations within a single instruction cycle, thereby improving processing speed while managing complexity through structured register organization
Solution Approach 2:
The patent introduces a new dimension of parallelism by using SIMD (Single Instruction Multiple Data) architecture, where a single instruction operates on multiple data elements simultaneously across parallel execution paths, transforming sequential processing into parallel processing without fundamentally changing the SHA-1 algorithm logic
2Productivity
If multiple execution unit processors are used, then processing capacity increases, but the requirement for multiple cycles to perform round calculations, rotates, and XORs still limits efficiency
Solution Approach 1:
The patent performs preliminary actions by pre-loading message inputs into 128-bit registers and pre-organizing state variables in 160-bit registers before the main processing loop, allowing the actual round calculations to proceed without repeated memory access overhead and reducing the cycles required per operation
Solution Approach 2:
The patent ensures continuity of useful action by maintaining all necessary state variables and message inputs in fast register storage throughout the 80 rounds, eliminating idle cycles where data would need to be re-fetched from memory, thereby keeping the processing pipeline continuously filled and maximizing throughput
Data Source
AI summary
A processor includes an instruction decoder to receive a first instruction to process a SHA-1 hash algorithm, the first instruction having a first operand to store a SHA-1 state, a second operand to store a plurality of messages, and a third operand to specify a hash function, and an execution unit coupled to the instruction decoder to perform a plurality of rounds of the SHA-1 hash algorithm on the SHA-1 state specified in the first operand and the plurality of messages specified in the second operand, using the hash function specified in the third operand.