Hardware Accelerator for SHA-2 Using Reduced Datapaths
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Solution Overview
Problem
The conventional implementation of Secure Hash Algorithm 2 (SHA-2) in devices requires significant circuit area and power due to the use of full datapaths, limiting its application in resource-constrained devices such as small appliances and wearable computers.
Innovation Solution
A hardware cryptographic accelerator processes SHA-2 operations using reduced datapaths, allowing for SHA-2 operations to be performed efficiently in multiple cycles of each round, thereby reducing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full datapaths are used for SHA-2 implementation, then cryptographic security and correctness are maintained, but circuit area and power consumption increase significantly
Solution Approach 1:
The cryptographic hash function is divided into multiple rounds, with each round processing a portion of the data through segmented datapaths. The data is partitioned into chunks that are processed sequentially through smaller datapath units, achieving the same cryptographic result while reducing the area of each individual datapath component.
Solution Approach 2:
The datapath width is made dynamic and adaptive, adjusting the datapath size based on the specific cryptographic operation being performed. The system can switch between different datapath configurations (e.g., 32-bit, 64-bit, or reduced widths) depending on the algorithm requirements, allowing area optimization without sacrificing security for operations that don't require full precision simultaneously.
2Reliability
If full datapaths are used for SHA-2 implementation, then cryptographic security and correctness are maintained, but power consumption increases significantly
Solution Approach 1:
The computation is segmented into multiple rounds and stages, with each stage using a reduced datapath. By processing data in smaller chunks through segmented computational units rather than maintaining a full-width datapath throughout, the power consumption of each active component is reduced while the cumulative security strength is maintained through the multiple processing passes.
Solution Approach 2:
The cryptographic processing is organized into periodic rounds, where reduced datapaths are activated in sequence rather than simultaneously. Each round processes a portion of the data through the reduced datapath, then deactivates before the next round begins, reducing the instantaneous power consumption while maintaining the overall cryptographic security through the accumulation of multiple processing rounds.
3Area of stationary object
If reduced datapaths are used, then circuit area and power consumption are reduced, but processing time increases due to multiple cycles per round
Solution Approach 1:
The data is segmented into multiple chunks that can be processed in parallel through the reduced datapath. By dividing the input data into separate blocks that are processed simultaneously in different processing units or pipeline stages, the total processing time is reduced despite using smaller datapaths, as the parallel processing compensates for the additional cycles required per individual data chunk.
4Area of stationary object
If reduced datapaths are used, then circuit area and power consumption are reduced, but device complexity increases due to multi-cycle processing control
Solution Approach 1:
The control logic is designed as a universal state machine that manages multiple datapath configurations and processing modes through a single integrated control unit. This multi-functional controller can adapt to different cryptographic algorithms and datapath widths without requiring separate control circuits for each configuration, reducing the overall device complexity despite the multi-cycle processing requirements.
Data Source
AI summary
In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of digest words in a plurality of digest registers; perform a plurality of rounds of the cryptographic hash algorithm, where the plurality of rounds is divided into first and second sets of rounds; in each cycle of each round in the first set, use W bits from the first digest register for a first function and use N bits from the second digest register for a second function; in each cycle of each round in the second set, use W bits from the second digest register for the first function and use N bits from the first digest register for the second function. Other embodiments are described and claimed.