SHA-2 Instruction Set Architecture for High-Speed Hashing
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Solution Overview
Problem
Conventional software solutions for implementing SHA-2 secure hashing algorithms require multiple instructions for each addition and logical shift/rotate operation, leading to inefficiencies and higher cycle counts, limiting the performance of SHA-256 operations.
Innovation Solution
A new instruction set architecture (ISA) is introduced that performs multiple rounds of SHA-2 operations with a single instruction, utilizing wide registers to store state variables and message inputs, enabling parallel processing and reducing the time required for SHA-2 round functions through optimized pipeline management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional software solutions use standard instructions for SHA-2 operations, then implementation is straightforward using available instructions, but the processing speed is limited to 15 cycles per byte with a theoretical limit of 9 cycles per byte
Solution Approach 1:
The SHA-2 algorithm is divided into distinct functional segments: message scheduling operations (computing s0, s1, and w[i]) and round operations (computing Ch, Ma, Σ0, Σ1). Each segment can be executed with optimized instruction sequences, allowing independent optimization of each phase while maintaining overall algorithm integrity.
Solution Approach 2:
Message scheduling operations are performed in advance before the main round operations begin. The values s0, s1, and w[i] are pre-computed and stored, eliminating the need to recalculate them during each round. This preliminary computation reduces the critical path length and improves overall processing speed.
2Manufacturing precision
If multiple instructions are used for each addition and logical shift/rotate operation, then precise implementation of SHA-2 algorithm is achieved, but the cycle count increases and performance decreases
Solution Approach 1:
Multiple operations are merged into single instruction sequences where possible. For example, the computation of s0 combines three rotate operations and two XOR operations into an optimized sequence that executes more efficiently than separate instructions. Similarly, round operations combine multiple additions, rotates, and logical operations into streamlined instruction flows.
Solution Approach 2:
The instruction sequence is dynamically optimized based on the specific SHA-2 variant (SHA-224, SHA-256, SHA-384, or SHA-512). The processor can switch between different optimized instruction sequences depending on which algorithm is being executed, allowing each variant to run at its maximum theoretical performance.
3Reliability
If the critical path includes four consecutive propagate additions with complex logical and rotation functions, then SHA-2 security requirements are met, but the computation time per round increases
Solution Approach 1:
Complex logical functions (Ch and Ma) and rotation operations (Σ0 and Σ1) are pre-computed during the message scheduling phase. By preparing these values in advance, the critical path during round operations is reduced to primarily additions, significantly decreasing the time required for each round while maintaining the full security properties of the algorithm.
Data Source
AI summary
A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.