SHA-2 Hashing Pipeline With Three-Block State Update

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Solution Overview

Problem

Existing SHA-2 hashing algorithms struggle with throughput limitations, particularly in high-frequency processor environments, requiring multiple cycles per round and excessive hardware resources, which is inefficient for single-message processing.

Innovation Solution

Partitioning the SHA-2 state update into three pipelined blocks with concurrent 1-cycle loops and feedback loops that send data 'back-in-time', allowing for efficient computation with minimal hardware overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing SHA-2 hashing algorithms are implemented in high-frequency processor environments, then cryptographic security is maintained, but throughput is limited due to requiring multiple cycles per round and excessive hardware resources

Engineering Contradiction:
ImprovethroughputVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The SHA-2 state update function is partitioned into three separate blocks (first block for variables A-D, second block for variables E-H, third block for temporary word computation). Each block can be executed independently in a pipelined manner, allowing concurrent execution across multiple cycles and improving throughput without requiring excessive hardware resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic pipelining where the three blocks are executed in overlapping time periods with feedback loops that feed results back to earlier stages. The first block of cycle N feeds into the second block of cycle N+1, which feeds into the third block of cycle N+2, creating a dynamic pipeline that maintains continuous operation at 1-cycle per round performance.

Inventive Principle:
Principle #15Dynamics

2Speed

If multiple cycles per round are used in existing SHA-2 implementations, then computation accuracy is ensured, but processing speed decreases

Engineering Contradiction:
Improveprocessing speedVSAvoidcomputation time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs preliminary partitioning of the state update function into three blocks before execution, preparing the computational structure in advance. This allows the processor to execute each block in a single cycle with proper pipelining, eliminating the need for multiple cycles per round while maintaining computation accuracy through the structured feedback loops.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipelined execution model ensures continuous useful action by overlapping the execution of three blocks across consecutive cycles. While the first block executes in cycle N, the second block executes in cycle N+1, and the third block executes in cycle N+2, creating uninterrupted computational flow that achieves 1-cycle per round effective throughput.

Inventive Principle:
Principle #20Continuity of useful action

3Use of energy by moving object

If existing SHA-2 implementations are deployed, then cryptographic hashing functionality is provided, but power consumption increases due to excessive hardware resources

Engineering Contradiction:
Improvepower consumptionVSAvoidthroughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

By segmenting the state update into three distinct blocks that can be executed sequentially with pipelining, the patent reduces the instantaneous hardware resource requirements compared to traditional parallel implementations. This segmentation allows the same functionality to be achieved with lower power consumption while maintaining throughput through continuous pipelined execution.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12556368B2High throughput data flow for SHA-2 hashing module
Publication Date: 2026.02.17 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12556368B2 patent drawing
  • US12556368B2 patent drawing
  • US12556368B2 patent drawing

AI summary

Provided are a method, a system, a computer program product, an Application Specific Integrated Circuit, and a cryptographic module, where a partitioning is performed of a SHA-2 state update into three blocks. A set of operations associated with the three blocks are executed in a pipelined manner, where each block feeds back for computation into itself.