SHA-2 SIMD Instruction Set Architecture for Hashing Efficiency
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Solution Overview
Problem
Conventional software solutions for implementing SHA-2 secure hashing algorithms require separate instructions for each addition and logical shift/rotate operation, leading to inefficiencies and a lack of efficient methods for performing SHA-256 operations, which are computationally complex and time-consuming.
Innovation Solution
A new instruction set architecture (ISA) is introduced that allows for SHA-2 operations to be performed using a single instruction multiple data (SIMD) instruction, utilizing registers with at least 256 bits to store state variables and message inputs, enabling parallel execution of SHA-2 round operations and optimizing the computation by reducing the time required for each round.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional software solutions using standard instructions are used to implement SHA-2 operations, then each addition and logical shift/rotate operation can be performed with individual instructions, but the computation time increases and efficiency decreases
Solution Approach 1:
The patent combines multiple SHA-2 round operations into a single SIMD instruction that processes multiple data elements in parallel. Instead of using separate instructions for each addition, rotation, and logical operation, the invention merges these operations into unified vector instructions that operate on multiple state variables simultaneously, thereby reducing the total number of instructions and improving computation efficiency
Solution Approach 2:
The patent transitions from scalar processing to vector processing by introducing SIMD (Single Instruction Multiple Data) operations. This dimensional change allows the processor to handle multiple 32-bit or 64-bit data elements in parallel using the same instruction, effectively adding a parallel processing dimension to the traditional sequential SHA-2 computation
2Productivity
If separate instructions are used for each SHA-2 operation, then implementation is straightforward using standard instructions, but the throughput rate remains limited
Solution Approach 1:
The patent creates universal SIMD instructions that can perform multiple SHA-2 round operations with different parameters (rotation amounts, shift amounts, logical operations) through a single instruction format. These multi-functional instructions can be configured to execute various SHA-2 variants (SHA-224, SHA-256, SHA-384, SHA-512) by adjusting the operating parameters rather than requiring separate dedicated instructions for each operation type
3Speed
If standard instructions are used for SHA-256 implementation, then the algorithm can be executed, but the cycle per byte approaches the theoretical limit and cannot be improved further
Solution Approach 1:
The patent performs preliminary preparation of message schedule inputs using SIMD operations before the main SHA-2 round processing. By pre-computing and organizing the message schedule data in parallel using vector instructions, the invention reduces the computational burden during the actual round operations, allowing for faster overall execution and breaking the conventional cycles-per-byte barrier
Data Source
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AI summary
A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.