SHA-256 Hash Circuit Pipeline Optimization for Bitcoin Mining
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Solution Overview
Problem
The existing SHA-256 hash algorithm implementation in Bitcoin mining machines faces challenges in achieving a low power consumption to hash rate ratio due to significant computation latency in the pipeline structure, particularly in the expansion data operation logic, which limits operation speed and increases energy costs.
Innovation Solution
The proposed circuit and method optimize the hash algorithm by reducing the number of operation logic stages required for computing expansion data through direct connections between expansion registers, allowing parallel processing and reducing computation latency, thereby improving operation speed and achieving a lower power consumption to hash rate ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional pipeline structure with multiple operation logic stages is used for SHA-256 hash algorithm, then computation can be performed systematically, but computation latency increases and operation speed decreases
Solution Approach 1:
The pipeline is divided into multiple operation stages (first operation stage, second operation stage, etc.), each handling specific expansion data computation tasks. This segmentation allows parallel processing of different expansion data, reducing overall computation latency while maintaining systematic computation flow.
Solution Approach 2:
Expansion data operation logic modules perform computations in advance for subsequent operation stages. By pre-computing expansion data that will be needed in future stages, the system reduces idle time and computation latency when those stages execute, thereby improving overall operation speed.
2Reliability
If more operation logic stages are added to compute expansion data, then computation completeness is improved, but device complexity increases and power consumption increases
Solution Approach 1:
Expansion data operation logic modules are designed to perform multiple functions: they compute expansion data for current stages and also prepare expansion data for future stages. This multi-functionality reduces the need for separate dedicated modules, simplifying the overall device complexity while maintaining computation completeness.
Solution Approach 2:
Multiple computation operations are merged into unified expansion data operation logic modules. Instead of having separate modules for different expansion data computations, the patent combines them into integrated modules that handle multiple tasks simultaneously, reducing device complexity while ensuring all computations are completed.
3Use of energy by moving object
If traditional sequential expansion data computation is used, then computation accuracy is maintained, but power consumption to hash rate ratio increases
Solution Approach 1:
The pipeline structure enables continuous computation where expansion data operation logic modules continuously generate and transfer expansion data through multiple operation stages without idle time. This continuous useful action maintains high hash rate while the efficient pipeline reduces power consumption per operation, improving the power consumption to hash rate ratio.
Solution Approach 2:
By pre-computing expansion data in advance during operation stages, the system avoids repeated computations and reduces the total energy required for hash rate generation. The preliminary computation of expansion data allows subsequent stages to execute faster with lower energy consumption, improving the efficiency ratio.
Data Source
AI summary
The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i−1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.