SHA-256 Message Scheduling Instruction Set Architecture
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Solution Overview
Problem
Existing instruction processing apparatuses face inefficiencies in performing SHA-256 secure hashing algorithms due to complex computational paths and limitations in processing multiple rounds within a single instruction cycle, particularly in 2-source processor architectures, leading to increased latency and throughput limitations.
Innovation Solution
A new instruction set architecture (ISA) is introduced that utilizes 128-bit registers and SIMD instructions to perform multiple rounds of SHA-256 operations within a 3-cycle pipeline, with specialized instructions for message scheduling to optimize the processing of SHA-256 round operations and message inputs, allowing for efficient computation of SHA-256 and SHA-512 algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SHA-256 implementation is used in 2-source processor architecture, then algorithm correctness is maintained, but processing latency increases and throughput decreases
Solution Approach 1:
The SHA-256 algorithm is segmented into distinct functional components: message scheduling operations (rotations, shifts, XORs) separated from the main compression function, and further divided into 64 rounds of iterative processing. This segmentation allows independent optimization of each segment, enabling parallel execution paths and reducing overall processing latency while maintaining algorithm correctness.
Solution Approach 2:
Message scheduling operations are performed in advance before the main compression function execution. The message schedule array is pre-computed with all required rotated and shifted values, allowing the compression function to proceed without waiting for intermediate calculations during each round, thereby reducing critical path latency and improving throughput.
2Speed
If multiple SHA-256 rounds are performed within a single instruction cycle, then processing speed increases, but computational complexity and resource requirements increase
Solution Approach 1:
Multiple SHA-256 rounds are merged into a single SIMD instruction execution. The instruction processes 4 parallel SHA-256 state transformations simultaneously using 128-bit registers, combining multiple computational paths into one unified operation that reduces instruction overhead and improves processing speed without proportionally increasing hardware complexity.
Solution Approach 2:
The SIMD instruction set is designed to be universal, supporting both SHA-256 and SHA-512 algorithms through the same hardware infrastructure. The same instruction encoding and execution units can process different hash algorithms by configuring appropriate register widths and operation sequences, reducing overall device complexity through multi-functionality.
3Productivity
If 128-bit SIMD registers are used for SHA-256 processing, then throughput increases, but compatibility with traditional 64-bit architectures decreases
Solution Approach 1:
The architecture transitions from traditional 64-bit scalar processing to 128-bit vector processing, adding a dimensional aspect to data handling. This allows parallel processing of multiple 32-bit words within a single 128-bit register, increasing throughput while maintaining backward compatibility through software abstraction layers that can emulate traditional behavior when needed.
Data Source
AI summary
A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.