SHA3-PAR Instruction for Keccak Parity Computation
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Solution Overview
Problem
Existing processor architectures face inefficiencies in executing SHA3/Keccak operations, which are critical for post-quantum cryptography, due to high computation times spent on complex bit manipulations and byte reordering within the Keccak state.
Innovation Solution
New instructions such as SHA3-PAR, SHA3-TXR1, SHA3-TXR2, SHA3-PI, SHA3-CHI1, and SHA3-CHI2 are introduced to accelerate internal sub-operations of the SHA3/Keccak round function, utilizing AVX2 registers to enhance 64-bit parity computations, atomic execution of Theta and Rho steps, byte rearrangements, and efficient Chi step computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processor architectures execute SHA3/Keccak operations using standard instructions, then the processor can maintain compatibility with existing instruction sets, but the execution time for complex bit manipulations and byte reordering becomes excessively long
Solution Approach 1:
The patent segments the SHA3/Keccak algorithm into distinct operational components (parity calculations, transform operations, byte reordering) and implements dedicated instructions for each segment. This allows each operation to be optimized independently, reducing the overall execution time while maintaining the integrity of the complete algorithm.
Solution Approach 2:
The patent introduces new intermediary instructions (SHA3-PAR, SHA3-TXR1, SHA3-TXR2, SHA3-PI, SHA3-CHI1, SHA3-CHI2) that act as mediators between the standard processor architecture and the SHA3/Keccak algorithm. These intermediary instructions bridge the gap by providing optimized execution paths for complex operations without requiring changes to the fundamental processor architecture.
2Productivity
If new specialized instructions are introduced to accelerate SHA3/Keccak operations, then execution latency is significantly reduced, but the processor instruction set becomes more complex
Solution Approach 1:
The patent designs the new instructions to be universally applicable to SHA3/Keccak operations while maintaining compatibility with existing processor architectures. The instructions are crafted to handle multiple operations efficiently (e.g., combining parity calculations with transform operations in single instructions), thereby reducing overall complexity despite the added functionality.
Solution Approach 2:
The patent utilizes parameter changes in the instruction set architecture, such as using AVX2 registers to enhance 64-bit parity computations and enabling atomic execution of Theta and Rho steps. By changing execution parameters and leveraging existing register architectures, the patent achieves acceleration without proportionally increasing instruction set complexity.
3Reliability
If atomic execution of Theta and Rho steps is implemented, then computation accuracy is improved, but the hardware requirements and instruction complexity increase
Solution Approach 1:
The patent implements atomic execution of Theta and Rho steps through self-service mechanisms where the instructions themselves ensure correct execution without requiring external hardware synchronization or complex memory management. The atomicity is achieved through the instruction design and execution model, allowing the processor to maintain accuracy while avoiding additional hardware complexity.
Data Source
AI summary
A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.