Shader Compiler Optimization for Memory Reduction Operations

The patent introduces a shared register file as an intermediary structure between threads and memory. Instead of threads directly accessing memory for data exchange, they use the shared register file which is accessible by multiple threads. This mediator provides fast access (comparable to register operations) while enabling data sharing between threads, thus resolving the contradiction between data sharing capability and execution performance.

The patent extends the compiler's optimization capability to serve multiple functions: it maintains SIMD instruction optimization for single threads while adding multi-thread optimization through subgroup detection and analysis. The compiler now performs dual analysis - traditional SIMD analysis and subgroup-based analysis - allowing it to generate optimized code that leverages both single-thread SIMD efficiency and multi-thread data locality, thus achieving universality in optimization scope.

The patent implements automatic subgroup detection and optimization in the compiler, making the system self-serve the optimization need. Instead of requiring authors to explicitly use subgroup extensions, the compiler automatically analyzes the shader code, detects reduction opportunities, and applies subgroup-based optimizations transparently. This self-service approach maintains high reduction performance while eliminating the complexity of explicit subgroup usage requirements.

The patent applies local quality optimization by making synchronization local rather than global. Instead of inserting memory barriers that synchronize all threads globally, the optimization uses subgroup-based reductions that only require synchronization within the subgroup. This localized approach maintains correctness for the reduction operation while avoiding unnecessary global synchronization overhead, thus improving performance while preserving reliability.