Shader Compiler Mitigating Power Rail Voltage Transients
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Solution Overview
Problem
Current integrated circuits face significant design challenges due to large current transients on power rails, which cause substantial voltage transients, leading to performance issues and potential data loss, especially in portable and mobile devices, where minimizing die area and maintaining performance is crucial.
Innovation Solution
A computing system with a first processing circuit and a second parallel data processing circuit, equipped with a shader compiler, modifies instruction sequences to mitigate current transients by inserting low-power instructions and optimizing power bins, thereby reducing the time rate of current change and minimizing voltage transients on the power rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large current transients are drawn from the power rail in a short amount of time, then the processing speed and performance are improved, but large voltage transients occur on the power rail causing data loss and performance degradation
Solution Approach 1:
The shader compiler performs preliminary action by analyzing the shader program and inserting dummy instructions before high-current transient operations. These dummy instructions are executed first to charge up the power rail capacitance, creating a buffer that absorbs the subsequent current transient and prevents voltage drops during the actual processing operation.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of dummy instructions that act as a mediator between the power supply and the shader processing operations. These dummy instructions serve as a buffer that decouples the immediate current demand from the power rail, allowing high-speed processing without direct voltage transient effects.
2Reliability
If capacitors are placed on the power rail to reduce voltage transients, then voltage stability is improved, but the die area increases significantly
Solution Approach 1:
The patent replaces the physical mechanical solution (adding capacitors to the power rail) with a software-based solution through the shader compiler. Instead of using hardware capacitors to store energy and smooth voltage transients, the system uses compiler-generated dummy instructions to manage power transient effects, eliminating the need for additional physical components and saving die area.
Solution Approach 2:
The dummy instructions serve as an intermediary software layer that replaces the need for physical capacitor intermediaries. Rather than relying on hardware energy storage components, the system uses instruction-level mediation to manage power transient effects, achieving voltage stability without additional die area consumption.
3Reliability
If the operational clock frequency is adjusted to reduce voltage transients, then voltage stability is improved, but the processing performance and throughput are reduced
Solution Approach 1:
The shader compiler performs preliminary analysis and insertion of dummy instructions before the actual processing begins. This preliminary action prepares the power rail by charging capacitance in advance, allowing the system to maintain high clock frequencies without voltage transient issues, thus preserving processing throughput while improving voltage stability.
Solution Approach 2:
The dummy instructions act as an intermediary mechanism that allows the system to operate at high clock frequencies without direct voltage transient effects. By mediating the power transient delivery through these instructions, the system maintains both high processing throughput and voltage stability, eliminating the need to reduce clock frequency.
Data Source
AI summary
An apparatus and method for efficiently managing voltage transients on a power rail caused by current transients of an integrated circuit. In various implementations, a computing system includes a processing circuit that executes instructions of a compiler that includes a current transients mitigator. When executing the instructions of the current transients mitigator, the processing circuit generates an estimate of a time rate of current flow being drawn from or returned to the power rail based on instruction types of a first sequence of instructions. Based on the estimate exceeds a threshold, the processing circuit replaces the first sequence of instructions with a second sequence of instructions that provides a smaller estimate. The second sequence is issued to the one or more compute circuits that utilize the power rail, rather than the first sequence.