Parallel Shader Exclusive Control via Execution Order Counter
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Solution Overview
Problem
Conventional methods that remove the Read-Modify-Write (RMW) function from the pixel shader limit the variety of pixel operations, preventing repeat operations such as outputting intermediate results to the frame buffer and reading them for further processing, which is necessary for executing complex shading algorithms and sophisticated arithmetic processing like image processing.
Innovation Solution
A rendering processing apparatus with a rasterizer generating pixels, a shader performing arithmetic processing in parallel, and an exclusive control part that updates an execution order counter and manages lock requests to ensure the order of execution among arithmetic processing parts, allowing for efficient exclusive control over parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RMW function is removed from the pixel shader to achieve exclusive control, then exclusive control over pixel operations is improved, but the variety of pixel operations is worsened
Solution Approach 1:
The patent merges the RMW function back into the pixel shader while maintaining exclusive control through a counter-based mechanism. The pixel shader now includes both arithmetic processing units and RMW units that share the same pixel buffer, with the exclusive control achieved through counter comparison rather than physical separation.
Solution Approach 2:
The patent introduces a counter as an intermediary mechanism to mediate between multiple arithmetic processing parts and the pixel buffer. This counter acts as a mediator that tracks execution order and enables exclusive control without requiring physical separation of RMW functions.
2Productivity
If multiple arithmetic processing parts perform operations on identical pixels in parallel, then processing efficiency is improved, but operation consistency is worsened
Solution Approach 1:
The patent performs preliminary action by assigning execution order counters to arithmetic processing parts before they access the pixel buffer. This preliminary counter assignment establishes the execution sequence in advance, ensuring that operations are performed consistently even when multiple parts process identical pixels in parallel.
Solution Approach 2:
The patent implements feedback by having arithmetic processing parts compare their execution order counters with the current counter value before accessing the pixel buffer. This feedback mechanism ensures that only the part with the highest counter value can perform RMW operations, maintaining operation consistency while allowing parallel processing.
Data Source
AI summary
A DDA 34 notifies the coordinates of a rasterized pixel to an exclusive control part 40, acquires a unique identification number associated with the pixel position from the exclusive control part 40, and adds the identification number to pixel data and supplies it to a shader 20. A plurality of shader pipes 22 in the shader 20 perform arithmetic processing for rendering pixels in parallel, and writes the processing results to a frame buffer 50. When performing an arithmetic instruction that requires exclusive control over a pixel, each shader pipe 22 issues a request to lock the pixel by notifying the identification information added to that pixel to the exclusive control part 40. If the lock request is accepted, the shader pipe 22 performs the arithmetic processing on that pixel. If the lock request is rejected, the shader pipe suspends and puts the arithmetic processing on that pixel into a wait state, and executes arithmetic processing on another pixel in the interim.