Shader L1 Cache Matrix Storage for Bandwidth Reduction
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Solution Overview
Problem
Existing data processing methods for structured buffers in graphics and computer pipelines are inefficient due to high bandwidth usage by invalid data and complex control logic, leading to reduced performance and increased hardware costs.
Innovation Solution
A data process apparatus and method that stores a to-be-cached matrix with elements in order, allowing the shader level-1 cache to directly access and process the matrix without element selection, reducing bandwidth footprint and idle clock cycles, and requiring a smaller shader level-1 cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If elements are stored in row-major order in structured buffer, then memory layout is simple, but shader must select elements which increases complexity and reduces access efficiency
Solution Approach 1:
The patent inverts the conventional approach by storing matrix elements in column-major order in the structured buffer instead of the typical row-major order. This inversion allows the shader to directly access contiguous memory locations without element selection logic, transforming the problem from one requiring complex control logic to one with simple sequential access. The column-major storage layout aligns with the shader's processing needs, eliminating the need for element selection while maintaining memory efficiency.
2Speed
If shader level-1 cache size is increased to store more matrix data, then data access speed improves, but hardware cost increases
Solution Approach 1:
The patent changes the data storage parameter from row-major to column-major order, which fundamentally alters how data is laid out in memory. This parameter change enables the shader to access required elements through simple sequential memory access without needing to select or skip elements. As a result, the shader level-1 cache can be smaller because it doesn't need to accommodate complex element selection logic and can work with a more compact data layout, reducing hardware cost while maintaining fast access speed.
3Measurement precision
If element selection is implemented in shader to access specific matrix elements, then data processing precision is maintained, but bandwidth footprint of invalid data increases
Solution Approach 1:
The patent extracts only the necessary matrix elements from the structured buffer by storing them in column-major order, which places required elements in contiguous memory locations. This extraction approach eliminates the need to read and then discard invalid data elements. The shader receives only the valid data it needs through simple sequential access, maintaining full data processing precision while minimizing the bandwidth footprint by eliminating invalid data transmission entirely.
Data Source
AI summary
The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix. The data process apparatus can improve the efficiency of accessing the internal memory unit and reduce the bandwidth occupied by invalid data; enable hardware pipelines to be tighter and reduce idle clock cycles; and enable the shader level-1 cache to be smaller, thereby reducing hardware costs.