Shader Recompilation for External Memory Bandwidth Reduction

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Solution Overview

Problem

In graphics processing systems, especially in mobile and embedded devices, the constrained external memory bandwidth leads to performance bottlenecks and increased energy consumption due to frequent data reads from external memory during rendering operations.

Innovation Solution

The method involves analyzing shaders to determine if they sample buffers at coordinates matching the current fragment location and recompiling them to read from on-chip registers instead of external memory, reducing the need for external memory access and optimizing render operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If shaders read buffer data at current fragment location coordinates, then rendering accuracy is maintained, but external memory bandwidth consumption increases

Engineering Contradiction:
Improverendering accuracyVSAvoidexternal memory bandwidth
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent introduces on-chip registers as an intermediary storage layer between external memory and the shader execution unit. By storing buffer data in these registers before rendering, the system maintains rendering accuracy while reducing external memory bandwidth consumption, as the registers act as a mediator that provides fast local access to frequently needed data.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by pre-loading buffer data into on-chip registers before the rendering operation occurs. This allows the shader to read from registers during rendering rather than accessing external memory, thereby maintaining rendering accuracy while reducing external memory bandwidth consumption.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If frequent data reads from external memory are performed during rendering, then complete buffer sampling is achieved, but power consumption increases

Engineering Contradiction:
Improvebuffer sampling completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The on-chip registers serve as an intermediary that stores buffer data locally, enabling complete buffer sampling to be achieved through register reads rather than external memory reads. This maintains sampling completeness while significantly reducing power consumption associated with external memory access.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By pre-loading buffer data into on-chip registers before rendering, the system ensures complete buffer sampling can be achieved using low-power register reads instead of high-power external memory reads, thus reducing overall power consumption while maintaining sampling completeness.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If external memory access is minimized, then energy consumption decreases, but data availability for rendering may be reduced

Engineering Contradiction:
Improveenergy consumptionVSAvoiddata availability
Core Design Contradiction:
Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The on-chip registers act as an intermediary storage layer that maintains data availability for rendering operations. By storing buffer data in these registers, the system ensures sufficient data is available for rendering while minimizing external memory access and associated energy consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The preliminary action of pre-loading buffer data into on-chip registers ensures data availability for rendering without requiring frequent external memory accesses. This approach maintains adequate data availability while significantly reducing energy consumption from external memory transactions.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If shaders are recompiled to use register coordinates, then rendering efficiency improves, but compilation time increases

Engineering Contradiction:
Improverendering efficiencyVSAvoidcompilation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the shader compilation process adaptive - shaders are recompiled only when necessary (e.g., when buffer binding changes or coordinate systems need adjustment) rather than being statically recompiled every frame. This dynamic approach improves rendering efficiency while minimizing the time loss from compilation operations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240371071A1Rendering optimisation by recompiling shader instructions
Publication Date: 2024.11.07 IMAGINATION TECH LTD
  • US20240371071A1 patent drawing
  • US20240371071A1 patent drawing
  • US20240371071A1 patent drawing

AI summary

A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.