Shader Sorter for Divergent Shader Execution

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Solution Overview

Problem

Current graphics processing technologies face inefficiencies in executing divergent shaders, particularly in parallel processing, due to limitations in SIMD lane management and register pressure, leading to suboptimal performance and increased power consumption.

Innovation Solution

The approach involves segmenting shader code into subroutines that can be executed in parallel, using a call stack and shader sorter to manage SIMD lanes coherently, and identifying sub-segments for parallel execution, thereby reducing register pressure and improving execution efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If divergent shaders are executed using traditional SIMD parallel processing, then processing throughput is maintained, but register pressure increases and execution efficiency deteriorates

Engineering Contradiction:

Improveshader execution efficiencyVSAvoidregister pressure

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments shader code into multiple subroutines that can be executed independently and in parallel. Each subroutine processes a specific portion of the shader logic, allowing the execution unit to manage register usage more efficiently by resetting or reusing registers between subroutine executions, thereby reducing overall register pressure while maintaining productivity.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If divergent branches are executed sequentially to reduce register pressure, then register usage is optimized, but execution time increases

Engineering Contradiction:

Improveregister usageVSAvoidexecution time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by sorting and organizing shader invocations into groups that can be executed in parallel batches. The shader sorter prepares the execution schedule in advance, identifying which subroutines can run simultaneously, thus enabling the system to maintain low register usage while minimizing execution time through optimized parallelization.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If more SIMD lanes are allocated to handle divergent shaders, then processing capacity increases, but power consumption increases

Engineering Contradiction:

Improveprocessing capacityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by activating only the necessary number of SIMD lanes for each batch of shader invocations rather than keeping all lanes continuously active. The execution unit dynamically adjusts the number of active lanes based on the current workload and subroutine being executed, thereby maintaining processing capacity when needed while reducing power consumption during lighter or register-sensitive phases.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11776195B2Techniques to manage execution of divergent shaders

Publication Date: 2023.10.03 INTEL CORP

AI summary

Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.