Shader Thread Workload Merging for Graphics Engine Load Balancing

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Solution Overview

Problem

Highly detailed 3D graphics models require significant system resources, leading to processing limitations as the number of polygons and vertices increases, which can be addressed by implementing hardware-accelerated tessellation and load balancing of shader core workloads to optimize performance.

Innovation Solution

The implementation of a graphics engine with runtime merging of shader execution threads and programmable pipeline stages allows for custom configuration of graphics hardware, balancing thread loads across shader cores to enhance system performance through multi-threaded execution and Single Instruction Multiple Data (SIMD) operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If hardware-accelerated tessellation is implemented to create geometrically complex 3D objects, then geometric detail and object complexity are improved, but system resource consumption and processing load increase

Engineering Contradiction:
Improvegeometric detailVSAvoidprocessing capability
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent divides the tessellation processing workload into multiple independent shader threads that can be executed in parallel across multiple shader cores. Each thread handles a portion of the tessellation calculations, allowing the system to process complex geometric models by breaking them down into manageable segments that can be distributed across available hardware resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple shader threads onto fewer shader cores when thread utilization becomes unbalanced. This consolidation allows the system to maintain high utilization of available cores by combining workloads, ensuring that processing capacity is efficiently used even when the total number of threads exceeds the number of physical cores.

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If the number of polygons and vertices is increased to achieve higher geometric detail, then object complexity is improved, but system bandwidth and processing limits are exceeded

Engineering Contradiction:
Improvegeometric detailVSAvoidsystem resources
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic load balancing that adjusts the distribution of shader threads across cores based on real-time utilization metrics. When certain cores become overloaded while others remain underutilized, the system dynamically redistributes threads to maintain balanced workloads, allowing the system to adapt to varying geometric complexity requirements without being constrained by fixed resource allocation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If multiple parallel shader cores are used to execute simultaneous threads, then processing throughput is improved, but thread load distribution becomes unbalanced

Engineering Contradiction:
Improveprocessing throughputVSAvoidthread load balance
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent employs a feedback mechanism that continuously monitors shader core utilization and uses this information to make load balancing decisions. The load balancer receives utilization data from shader cores, analyzes the distribution of workloads, and adjusts thread allocation accordingly, creating a closed-loop control system that maintains optimal performance across varying workloads.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9607353B2Load balancing and merging of tessellation thread workloads
Publication Date: 2017.03.28 DAEDALUS PRIME LLC
  • US9607353B2 patent drawing
  • US9607353B2 patent drawing
  • US9607353B2 patent drawing

AI summary

In one embodiment described herein, a graphics engine with shader unit thread load balancing functionality executes shader instructions from multiple execution threads in a smaller number of execution threads by combining instructions from multiple threads at runtime. In one embodiment, multiple shader unit threads containing less than a minimum number of instructions are combined to minimize the discrepancy between the shortest and longest thread. In one embodiment, threads are merged when they contain a common output register.