Shader Vectorization via Masked Predication for CPU Execution
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Solution Overview
Problem
Vectorization of shader code compiled for GPUs into CPU-executable form is non-trivial, especially with control flow logic, requiring efficient packing and transformation to exploit CPU vector instructions while maintaining high speed and minimizing code size for just-in-time compilation and compiler optimizations.
Innovation Solution
A vectorization process that analyzes and annotates operations, scopes, and control flow for predication and mask usage, applying transformation rules to produce vectorized Intermediate Representation (IR) code suitable for CPU execution, using mask management and blending operations to handle divergent control flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shader code is vectorized for CPU execution to exploit vector instructions, then performance increases up to W times, but the complexity of transforming and packing independent computations increases
Solution Approach 1:
The shader code is divided into multiple independent computation lanes that can be processed in parallel. Each lane handles a portion of the vector width W, allowing the complex transformation to be broken down into manageable segments that can be independently optimized and combined.
Solution Approach 2:
The vectorization transformation uses nested loops where outer loops handle different vector lanes and inner loops process individual elements. This nesting structure systematically organizes the complex transformation process, making it manageable and suitable for JIT compilation.
2Reliability
If control flow logic is preserved in vectorized shader code, then correctness is maintained, but execution divergence reduces performance benefits
Solution Approach 1:
Execution masks are introduced as intermediary data structures that track which elements are active in each vector lane. These masks mediate between the control flow logic and the vectorized execution, allowing conditional operations to be performed efficiently by selectively applying operations only to active elements without full divergence.
Solution Approach 2:
The transformation changes the parameter representation of control flow from scalar conditional jumps to vector-wide operations with mask parameters. This allows control flow to be expressed in a form that is compatible with vectorized execution, maintaining correctness while reducing divergence by processing multiple elements through the same control path.
3Quantity of substance
If IR code size is minimized for JIT compilation, then memory usage decreases, but the ability to perform traditional compiler optimizations is reduced
Solution Approach 1:
Vectorization-specific information such as lane masks and blending operations are extracted as separate metadata structures rather than being embedded throughout the IR code. This separation reduces the core IR code size while preserving optimization opportunities, as the extracted vectorization info can be processed independently by the JIT compiler.
Solution Approach 2:
Vectorization analysis and transformation information is computed in advance during the transformation pass and stored as pre-computed metadata. This preliminary action prepares the IR code for JIT compilation by pre-identifying optimization opportunities and vectorization parameters, enabling fast JIT compilation without sacrificing optimization capability.
Data Source
AI summary
Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.