Shadow CPU Core Layout for Area-Efficient Functional Safety
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Solution Overview
Problem
Existing lockstep systems for functional safety in computer processing units (CPUs) are inefficient in terms of area usage, as they often require identical cores operating at the same speed, which increases cost and power consumption without optimizing for area efficiency.
Innovation Solution
A network of processor cores is designed with a main core and a secondary shadow core, where the secondary core has a different physical design focused on area efficiency, operating at a lower clock frequency and simulating or refraining from performing certain operations to reduce physical size while maintaining error detection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical processor cores are used in lockstep systems to ensure functional safety, then reliability is improved, but area usage increases
Solution Approach 1:
The patent applies asymmetry by designing the secondary core with a different physical implementation than the main core. While both cores execute the same RTL description and maintain functional equivalence for safety checking, the secondary core uses area-optimized physical design rather than performance-optimized design, creating asymmetric physical characteristics that reduce overall area usage while maintaining reliability
Solution Approach 2:
The patent applies local quality by optimizing different parts of the system with different design priorities. The main core uses performance-optimized physical design for speed-critical operations, while the secondary core uses area-optimized physical design for safety monitoring. This localized optimization allows each component to be designed for its specific function, reducing total area while maintaining functional safety
2Reliability
If processor cores operate at the same clock frequency in lockstep mode, then functional safety is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock frequency adaptive rather than static. The system dynamically adjusts the clock frequency of the main core to match the secondary core's capability when operating in lockstep mode for safety-critical operations, and can operate at higher frequencies when safety monitoring is not required. This dynamic frequency adjustment reduces power consumption while maintaining functional safety when needed
3Reliability
If the secondary core performs all processes like the main core, then error detection capability is improved, but area efficiency deteriorates
Solution Approach 1:
The patent applies copying by having the secondary core implement only the essential functional logic needed for safety monitoring rather than a complete duplicate of the main core. The secondary core copies the critical path logic and state machine behavior sufficient for detecting errors, omitting redundant components such as full cache hierarchies, peripheral interfaces, and non-critical processing units, thereby reducing area while maintaining error detection capability
Data Source
AI summary
Systems and methods related to area-efficient functional safety are disclosed. A main core may have a first physical design and register transfer level (RTL) description. A secondary core may have a second physical design. The secondary core may have the same RTL description, but the first physical design may focus on performance and speed while the second physical design focuses on area-efficiency or low power. The secondary core may have a portion of the same RTL, but a different RTL description overall. The portion that is described by the same RTL may be an error prone portion of the main core. In either case, the secondary core may be physically smaller than the main core. The secondary core may be used to monitor for errors of the main core during operation. The main core may slow down when the main core and secondary core are operated in lockstep.