Shadow Data Register Copying for Non-Volatile Storage Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data storage systems for non-volatile storage arrays face inefficiencies in data transfer latency due to the need for multiple shadow data latches to receive data before it can be copied to corresponding write buffer latches, leading to increased data path time.
Innovation Solution
Implementing a system where a portion of the target data received by a shadow data register is copied to a corresponding write buffer data register before additional data is received by an adjacent shadow data register, reducing the need for explicit copy operations and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple shadow data latches are used to receive data before copying to write buffer latches, then data transfer completeness is ensured, but data transfer latency increases
Solution Approach 1:
The patent applies preliminary action by copying data from shadow data latches to write buffer latches as soon as each latch receives its data, rather than waiting for all latches to be filled. This early copying action reduces the overall data path time while ensuring data integrity through the dual-latch structure.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the data receiving process with the data copying process. While shadow data latches continue to receive incoming data, the system simultaneously copies data from filled shadow latches to write buffer latches, eliminating idle waiting time and maintaining continuous data flow.
2Reliability
If explicit copy operations are performed after data reception, then data integrity is maintained, but data path time increases
Solution Approach 1:
The patent eliminates idle time by making the copying operation concurrent with the data reception process. The system continuously receives data into shadow latches while simultaneously copying from completed shadow latches to write buffer latches, ensuring no time is wasted and data integrity is maintained through the structured latch architecture.
Solution Approach 2:
The patent performs the copying action preliminarily, initiating the transfer from shadow latches to write buffer latches as soon as data is received, rather than waiting for the complete data set to arrive. This preliminary copying maintains data integrity through the dual-latch verification mechanism while improving overall throughput.
3Device complexity
If data is copied only after all shadow latches are filled, then copying simplicity is maintained, but latency is increased
Solution Approach 1:
The patent applies preliminary action by initiating copy operations as soon as individual shadow latches receive their data, rather than waiting for all latches to be filled. This approach maintains relatively simple control logic while dramatically reducing the data path time by eliminating the waiting period for complete latch filling before copying begins.
Data Source
AI summary
Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.