Shadow DRAM CRC RAID Architecture for CXL Drive Bandwidth
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Solution Overview
Problem
Conventional RAID and chipkill solutions for DRAM systems face challenges such as high power consumption, increased cost, and bandwidth penalties due to write amplification, which affect reliability and availability in datacenter environments.
Innovation Solution
A shadow DRAM with a CRC+RAID architecture is introduced, functioning as a two-stage cache to mitigate write amplification, providing chipkill-level protection with low die and cost overheads by using a shadow DRAM before write operations in the main DRAM module, thus enhancing bandwidth and reducing redundancy overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RAID solution is used for error correction, then reliability is improved, but write amplification occurs which reduces bandwidth and increases power consumption
Solution Approach 1:
The patent segments the RAID protection mechanism into two distinct parts: a shadow DRAM that handles error correction data separately from the main DRAM that stores user data. This segmentation allows the main DRAM to operate at full bandwidth without being burdened by RAID write amplification, while the shadow DRAM handles the error correction overhead independently.
Solution Approach 2:
The shadow DRAM acts as an intermediary between the host and the main DRAM, absorbing the write amplification overhead for RAID error correction. This intermediary structure allows the main DRAM to provide high-speed data access while the shadow DRAM handles the slower, overhead-intensive error correction operations separately.
2Productivity
If chipkill design is used to reduce write amplification, then bandwidth is improved, but power consumption and die cost increase
Solution Approach 1:
The patent creates a copy structure where the shadow DRAM mirrors the error correction functionality of chipkill but with reduced overhead. Instead of duplicating entire DRAM chips for error correction as in chipkill, the shadow DRAM only stores the essential error correction data, reducing both power consumption and die cost while maintaining bandwidth performance.
3Productivity
If chipkill design is used to reduce write amplification, then bandwidth is improved, but die cost and redundancy overhead increase
Solution Approach 1:
The shadow DRAM is designed as a smaller, less expensive component compared to full chipkill implementation. It uses cheaper memory resources to provide the essential error correction functionality, reducing the overall die cost and redundancy overhead while maintaining the bandwidth benefits of reduced write amplification.
Data Source
AI summary
Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.