Shadow Feature ML for IC Capacitance Extraction
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Solution Overview
Problem
Modern integrated circuit (IC) designs are increasingly complex, leading to computationally burdensome and inefficient methods for determining capacitance values, such as rigorous simulation and phenomenological modeling, which struggle with accuracy and speed in parasitic capacitance extraction.
Innovation Solution
The implementation of shadow feature-based technology, which uses machine learning models trained on extracted shadow features from IC layouts to determine capacitance values, characterizing capacitive coupling effects through unitless scalar values, reducing dimensionality and computational intensity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If rigorous simulation or phenomenological modeling is used to determine capacitance values, then measurement precision is improved, but productivity deteriorates due to high computational requirements and lengthy calculation times
Solution Approach 1:
The system performs preliminary actions by extracting shadow features from IC layout components and using machine learning models to pre-determine capacitance values during the design stage, rather than performing rigorous simulations at the time of analysis. This advance preparation enables rapid capacitance determination without compromising accuracy.
Solution Approach 2:
The system creates simplified representations (shadow features) that copy essential geometric and spatial characteristics of IC layout components without replicating the full complexity of the original structures. These shadow features capture the necessary information for capacitance calculation while dramatically reducing computational requirements.
2Measurement precision
If rigorous simulation is used for parasitic capacitance extraction, then measurement precision is improved, but loss of time worsens due to immense computational demands
Solution Approach 1:
The system extracts only the essential shadow features from complete IC layouts, separating the critical geometric information needed for capacitance calculation from the full design complexity. This extraction process removes unnecessary computational burden while retaining the information required for accurate parasitic capacitance determination.
Solution Approach 2:
The system performs preliminary extraction of shadow features and capacitance value determination during the design flow, completing computationally intensive tasks in advance rather than during final analysis. This preliminary action eliminates lengthy calculation latencies when results are needed.
3Measurement precision
If conventional parasitic extraction methods are used, then measurement precision is improved, but device complexity worsens due to computationally burdensome processes
Solution Approach 1:
The system uses shadow features as simplified copies that represent IC layout components for capacitance calculation purposes. These shadow features replicate only the essential spatial and geometric properties needed for accurate capacitance determination, eliminating the need to process full design complexity.
Solution Approach 2:
The system segments the capacitance determination process into distinct stages: shadow feature extraction from layouts, machine learning model training on extracted features, and capacitance value prediction. This segmentation breaks down the complex overall process into manageable components that can be executed efficiently.
Data Source
AI summary
A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.