Shadow Latch MTCMOS Circuit for Low-Leakage Data Retention

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Solution Overview

Problem

Conventional multi-threshold CMOS (MTCMOS) sequential circuits face challenges in achieving low-power retention mode with low leakage currents while maintaining high-speed active mode operation, particularly due to poor performance and high leakage issues at low operating voltage levels.

Innovation Solution

The design incorporates a first latch circuit with transistors of a specific threshold voltage range for active mode operation and a second latch circuit with higher threshold voltage transistors for low-power retention mode, featuring a transfer gate and inverters powered from switchable voltage nodes, along with a control circuit for power management and forward biasing to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low threshold voltage transistors are used for active mode operation, then high-speed operation is achieved, but leakage current increases during standby operation

Engineering Contradiction:

Improveoperation speedVSAvoidleakage current

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The sequential circuit is divided into two separate latch circuits: a first latch circuit using low threshold voltage transistors for high-speed active mode operation, and a second latch circuit using high threshold voltage transistors for low-leakage standby mode operation. This segmentation allows each circuit to be optimized for its specific operating mode without compromise.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The circuit dynamically switches between two operational states by controlling the connection between the first and second latch circuits through transfer gates. During active mode, the first latch is connected and operational while the second latch is disconnected. During standby mode, the connection is reversed, allowing the circuit to adapt its characteristics based on operational requirements.

Inventive Principle:

Principle #15Dynamics

2Loss of energy

If high threshold voltage transistors are used for standby operation, then leakage current is reduced, but performance deteriorates during active mode operation

Engineering Contradiction:

Improveleakage currentVSAvoidoperation speed

Core Design Contradiction:

Loss of energyVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The high threshold voltage transistors in the second latch circuit are used only temporarily during mode transitions and primarily during standby operation, while the low threshold voltage transistors in the first latch circuit handle the demanding active mode operation. This allows each transistor type to be used in its optimal operating context.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Loss of energy

If conventional HVT-based retention flip-flops are used, then low-power retention is achieved, but robustness and performance are poor at low operating voltage levels

Engineering Contradiction:

Improvepower consumptionVSAvoidrobustness

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

Different regions of the circuit have different transistor threshold voltage characteristics optimized for their specific function. The first latch circuit uses low threshold voltage transistors with high mobility for robust operation at low voltages during active mode, while the second latch circuit uses high threshold voltage transistors for low leakage during standby mode. Each region's quality is tailored to its operational requirements.

Inventive Principle:

Principle #3Local quality

Data Source

PatentEP3195473B1Low leakage shadow latch-based multi-threshold CMOS sequential circuit

Publication Date: 2024.09.18 TEXAS INSTRUMENTS INC

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AI summary

In described examples, a multi-threshold CMOS (MTCMOS) sequential circuit (2) includes a first latch circuit (20) formed of transistors with threshold voltages in a first range, along with a second latch circuit (50) with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch (20) with power switching circuitry to selectively decouple inverters of the second latch circuit (50) from a voltage supply (VDDC) during low-power retention mode operation of the sequential circuit (2).