Shadow-Latch Pulse Flip-Flop for Lower Clock-to-Output Delay
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Solution Overview
Problem
Modern processors face inefficiencies in storing and driving data between pipeline stages due to high clock cycle periods caused by setup time and clock-to-output delay in flip-flop circuits, which limits design flexibility and increases latency.
Innovation Solution
A flip-flop circuit design incorporating a master latch, shadow latch, and bypass circuit, where the bypass circuit acts as a tri-state inverter to reduce clock-to-output delay by allowing both rising and falling data transitions to be included in the critical path when the clock signal is asserted, and using a pulse signal to determine transparency windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional flip-flop circuit is used between pipeline stages, then data storage and driving between stages is achieved, but the clock cycle period increases due to setup time and clock-to-output delay
Solution Approach 1:
The flip-flop circuit is segmented into a master latch and a shadow latch, each performing specific functions. The master latch captures data during the transparent phase while the shadow latch holds the previous value, allowing data to be transferred during the transparent phase rather than waiting for setup time, thus reducing the clock cycle period while maintaining reliable data storage
Solution Approach 2:
The circuit uses dynamic latching where the master latch transitions from opaque to transparent based on the clock signal phase. This dynamic behavior allows the circuit to accept data during the transparent phase and then lock it in during the opaque phase, enabling faster operation by eliminating the traditional setup time constraint
2Loss of time
If flip-flop circuits are designed for low latency by eliminating one input data transition, then clock-to-output delay is reduced, but design flexibility is reduced
Solution Approach 1:
The transparent flip-flop circuit is designed to accept both rising and falling edge transitions of the data input signal during its transparent phase. This multi-functionality allows the same circuit to handle different data transition types without requiring separate optimized circuits, thereby reducing clock-to-output delay while maintaining design flexibility for various data patterns
Data Source
AI summary
A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.