Shadow Logic Fault Testing via Delayed Test Patterns
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Solution Overview
Problem
Testing of shadow logic in integrated circuit (IC) chips is challenging due to its indirect access, making it difficult to identify faults, especially transition faults, which can cause delays in data exchange and affect the IC's functioning.
Innovation Solution
The method involves delaying test patterns by a time interval equivalent to the access time of the sequential block, allowing them to bypass the memory block and directly test the shadow logic for faults, using reference cells and reference row decoders to simulate the access time and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test patterns are directly applied to shadow logic without bypassing memory block, then fault detection capability is improved, but access time and test complexity increase
Solution Approach 1:
The test methodology is segmented into two distinct paths: one for testing memory block and another for testing shadow logic. By using control signals to bypass the memory block when testing shadow logic, the test process is divided into separate operational modes, allowing efficient testing of each component without unnecessary delays.
Solution Approach 2:
Control signals act as intermediaries to manage the test pattern flow. These control signals enable the test patterns to bypass the memory block and directly access the shadow logic through intermediate circuitry, reducing access time while maintaining fault detection capability.
2Measurement precision
If test patterns are delayed to match memory access time, then shadow logic testing accuracy is improved, but test time increases
Solution Approach 1:
The test system dynamically adjusts the test pattern timing based on the operational mode. When testing shadow logic, the system delays test patterns to match memory access time only when necessary, and uses bypass paths when speed is critical, making the test time dynamic rather than static.
Solution Approach 2:
The timing parameters of test patterns are changed based on the testing objective. By adjusting the delay time of test patterns to match memory access time only when required for accurate shadow logic testing, the system optimizes both measurement precision and test time.
3Device complexity
If conventional testing methods are used for shadow logic, then simplicity is maintained, but fault identification capability deteriorates
Solution Approach 1:
The shadow logic testing capability is extracted from the conventional memory testing path. By separating the shadow logic test path from the memory test path using control signals and bypass circuitry, the system can test shadow logic independently with dedicated test patterns, improving fault identification without significantly increasing overall system complexity.
4Reliability
If full memory access protocol is used for shadow logic testing, then comprehensive testing is achieved, but power consumption increases
Solution Approach 1:
Instead of always performing full memory access protocols, the system applies partial action by using bypass paths for shadow logic testing. This allows comprehensive testing of shadow logic without activating the entire memory access protocol, reducing power consumption while maintaining testing effectiveness.
Data Source
AI summary
A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.