Shadow Page Tables for Extended Memory Attributes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Open standard ISAs like RISC-V do not allow developers to redefine the format of page table entries to include all desired memory attributes, leading to performance issues due to the lack of space for additional attributes in the fixed PTE format.
Innovation Solution
Implement a system with a first and second page table, where secondary page table entries store additional memory attributes at a predetermined offset from the primary entries, allowing extended access to desired attributes without breaking compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed page table format from open standard Instruction Set Architectures is used, then compatibility is maintained, but the ability to store all desired memory attributes is limited
Solution Approach 1:
The page table is divided into two separate tables: a first page table storing primary page table entries with basic memory attributes, and a second page table storing secondary page table entries with additional memory attributes. This segmentation allows each table to have optimized formats while together providing comprehensive attribute storage without breaking compatibility with fixed-format standards.
Solution Approach 2:
Instead of expanding the width of page table entries in a single dimension, the solution adds a second dimension by introducing a second page table. The address translation module walks through the first page table and then accesses corresponding entries in the second page table, effectively stacking attribute storage in multiple layers to overcome format limitations.
2Adaptability or versatility
If additional memory attributes are stored in page table entries, then more complex applications can operate, but the fixed format of standard page tables cannot be redefined
Solution Approach 1:
The first page table maintains universal compatibility with standard Instruction Set Architecture formats, while the second page table provides extended functionality for additional memory attributes. Together, they form a multi-functional page table system that satisfies both compatibility requirements and extended attribute storage needs for complex applications.
Solution Approach 2:
The address translation module acts as an intermediary that manages the interaction between the two page tables. It walks through the first page table to identify primary entries, then uses that information to locate and retrieve corresponding secondary entries from the second page table, effectively mediating the access to combined attribute information without requiring changes to standard page table formats.
3Adaptability or versatility
If the page table entry format is extended to include more attributes, then memory management functionality is enhanced, but compatibility with standard architectures is broken
Solution Approach 1:
The page table functionality is segmented into two distinct tables with different purposes: the first page table maintains standard-compliant formats for compatibility, while the second page table provides extended attribute storage. This segmentation allows the system to reliably maintain architecture compatibility while simultaneously enhancing memory management functionality through the additional attributes in the second table.
Data Source
Figure 1~2C
Figure 2D~2G
Figure 3
AI summary
A computer system comprises a physical memory (406) storing a first (412) and a second (414) page table, and an address translation module (404). The first page table comprises primary page table entries, where each page table entry among the primary page table entries is configured to store a mapping of a virtual memory address to a physical memory address and auxiliary information. The second page table comprises secondary page table entries each storing at least one further auxiliary information, where each secondary page table entry corresponds to a primary page table entry in the first page table. The address translation module is configured to, in response to receiving a request from a processor, walk through the first page table to identify a primary page table entry and consecutively identify a location of a corresponding secondary page table entry based on a location of the primary page table entry.