Shadow Pointer Directory for Cache Hierarchy Synonym Conflicts
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Solution Overview
Problem
In computing systems with inclusive cache hierarchies, synonym conflicts arise due to the lack of knowledge by lower-level caches about the location of cache lines in higher-level caches, leading to reduced performance and the need for extra steps in translating absolute addresses, which can cause inefficiencies in cache coherence and cross-interrogation processes.
Innovation Solution
Implementing a shadow pointer directory (SPD) that maps each entry in the higher-level L1 cache to a corresponding location in the lower-level L2 cache, allowing the L2 cache to generate cross-interrogation vectors and filter requests effectively, thereby providing visibility and resolving synonym conflicts concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an inclusive cache hierarchy is used, then cache checking speed is improved, but synonym conflicts arise due to lack of knowledge by lower-level caches about higher-level cache locations
Solution Approach 1:
The patent introduces a shadow pointer directory (SPD) as an intermediary data structure in the lower-level cache (L2) that mediates between the inclusive cache hierarchy and the need for location tracking. The SPD contains shadow entries that map cache line locations in the upper-level cache (L1) to corresponding locations in the lower-level cache (L2), enabling L2 to track L1 locations without disrupting the inclusive cache architecture or requiring complex coordination protocols.
2Device complexity
If lower-level caches do not track higher-level cache locations, then cache hierarchy simplicity is maintained, but cross-interrogation efficiency is reduced
Solution Approach 1:
The patent implements a copying mechanism where the lower-level cache (L2) maintains a shadow copy of the upper-level cache (L1) location information in the shadow pointer directory. Instead of L2 actively tracking L1 locations through complex protocols, L2 simply copies the necessary location mapping information into shadow entries, enabling efficient cross-interrogation while keeping the overall hierarchy structure simple and the L2 cache design straightforward.
3Reliability
If extra translation steps are added to resolve synonym conflicts, then cache coherence is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the mapping between upper-level and lower-level cache locations in the shadow pointer directory before any conflict resolution is needed. When a synonym conflict occurs, L2 can immediately query the SPD to determine the corresponding L1 location without performing complex real-time translation or coordination, thus resolving cache coherence issues quickly without adding significant processing time.
Data Source
AI summary
A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.