Shadow Register Update via Intermediate Buffering
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Solution Overview
Problem
In processing units, shadow storage entities operating at a slower clock cycle often miss updates from the result bus due to the coincidence of clock edges, leading to unreliable and inefficient data transfer.
Innovation Solution
A processing unit with a first storage entity updated at a higher clock cycle, coupled with shadow storage entities via an intermediate storage entity and selection circuitry, buffers and prioritizes update information to ensure reliable transfer to shadow storage entities at their active clock edge, using multiple storage stages and prioritization to avoid data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If shadow storage entities operate at a slower clock cycle to match subunit speed, then power consumption and timing are improved, but update reliability deteriorates due to missed updates from the result bus
Solution Approach 1:
The patent applies preliminary action by capturing update information from the result bus at multiple intermediate storage stages before the shadow storage entity's slower clock edge arrives. The intermediate storage entity buffers updates that occur between slower clock cycles, ensuring no update is lost despite the clock frequency mismatch. This allows the shadow storage entity to operate at the slower clock cycle (improving power and timing) while maintaining update reliability through the preliminary buffering action.
Solution Approach 2:
The patent introduces an intermediate storage entity as a mediator between the result bus (operating at faster clock cycle) and the shadow storage entity (operating at slower clock cycle). This intermediary buffers and holds update information, allowing the faster result bus to write updates at its higher frequency while the slower shadow storage entity reads them at its lower frequency without missing any updates. The selection circuitry further mediates by selecting which stored update to transfer to the shadow storage entity at the appropriate slower clock edge.
2Reliability
If shadow storage entities run at core speed (first clock cycle), then update delivery is guaranteed, but timing and power consumption worsen
Solution Approach 1:
The intermediate storage entity performs preliminary buffering of update information at multiple storage stages, capturing all updates that occur between the slower shadow storage clock cycles. This preliminary action ensures that when the shadow storage entity's clock edge arrives, the latest update is already available, guaranteeing reliable update delivery without requiring the shadow storage entity to run at the faster core clock speed, thus reducing power consumption.
Solution Approach 2:
The intermediate storage entity acts as a mediator that decouples the clock domains of the result bus and shadow storage entity. It accepts updates at the faster core clock frequency and provides them to the shadow storage entity at the slower operating frequency, maintaining update delivery reliability while allowing the shadow storage entity to operate at lower power consumption appropriate for its actual operating speed.
3Loss of time
If shadow storage entities operate at slower clock cycle, then timing is improved, but update coincidence probability decreases to one out of N updates
Solution Approach 1:
The intermediate storage entity with multiple storage stages performs preliminary capture of update information at the faster clock cycle, storing successive updates in different stages. This preliminary action eliminates the need for coincidence between the faster result bus clock edges and the slower shadow storage clock edges, as updates are captured and held in the intermediate storage until the shadow storage entity is ready to receive them, improving timing while maintaining reliability.
Solution Approach 2:
The intermediate storage entity serves as a mediator that buffers updates between the faster result bus and the slower shadow storage entity. It decouples the timing between the two clock domains, allowing the shadow storage entity to operate at its optimal slower timing without worrying about clock edge coincidence. The selection circuitry then selects the appropriate buffered update to transfer to the shadow storage entity at its slower clock edge, ensuring reliable updates despite the timing mismatch.
Data Source
AI summary
A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.