Shadow Register Mapping for Efficient Multi-Register Access

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Central processors waste time repeatedly specifying register addresses when accessing multiple registers, leading to inefficiencies in timing and synchronization.

Innovation Solution

A storage device with a shadow register and controller that maps a shadow section to a register section, allowing data to be written or read directly through the shadow register when enabled, reducing the need for repeated address specification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the central processor specifies register addresses repeatedly to access multiple registers, then the register access can be performed, but the access time increases and processing efficiency decreases

Engineering Contradiction:

Improveregister access efficiencyVSAvoidtime for specifying register addresses

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a shadow register as an intermediary between the central processor and the actual register. The shadow register holds a copy of the register data and can be accessed directly by the processor without repeatedly specifying the original register address. This intermediary structure eliminates the time-consuming address specification process while maintaining data access functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The shadow register is pre-loaded with register data before the processor needs to access it. By performing the data copying action in advance (when the enable signal is active), the system prepares the data in the shadow register so that subsequent processor accesses can occur immediately without address specification delays.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the shadow register is mapped to the register section, then simultaneous access to multiple registers is improved, but the device complexity increases due to additional mapping control circuits

Engineering Contradiction:

Improvesimultaneous register access capabilityVSAvoidmapping control circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The mapping between the shadow register and register section is made dynamic rather than static. The mapping relationship changes based on the state of the enable signal - when enabled, the shadow register is mapped to the register section; when disabled, the mapping is removed. This dynamic approach allows the system to achieve simultaneous access capability only when needed, reducing the average complexity of the control circuitry.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11321091B2Storage devices mapped to registers and mapping methods thereof

Publication Date: 2022.05.03 NUVOTON

AI summary

A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.