Shadow Scan Decoder Multi-Core JTAG Efficiency
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Solution Overview
Problem
In multi-threaded, multi-core environments, existing methods require separate instructions to be loaded for each core to extract shadow scan data, which is inefficient and cumbersome.
Innovation Solution
A TAP-based method that utilizes the JTAG defined state machine to execute shadow scan instructions across one to multiple cores with a single load operation, eliminating the need for separate instructions for each core by processing a bit sequence including a thread identifier and core identifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate instructions are loaded for each core to extract shadow scan data, then the shadow scan data can be obtained from each core, but the testing process becomes cumbersome and inefficient
Solution Approach 1:
The patent combines multiple separate shadow scan instructions into a single integrated instruction that can simultaneously access shadow scan data from multiple cores. The instruction includes a core identifier field that can specify one or more cores, allowing the test access port controller to extract shadow scan data from multiple cores without loading separate instructions for each core, thereby improving testing efficiency while reducing instruction loading complexity
2Productivity
If a single shadow scan instruction is used for multiple cores, then the testing efficiency improves, but the instruction structure becomes more complex
Solution Approach 1:
The patent creates a universal shadow scan instruction structure that can function for a single core or multiple cores depending on the core identifier field configuration. The instruction format includes a core identifier field that can be set to specify individual cores or multiple cores, making the same instruction structure adaptable to different testing scenarios without requiring separate specialized instructions, thus improving efficiency while controlling structural complexity
Solution Approach 2:
The instruction structure is segmented into distinct fields including operation code, core identifier, and control bits. This segmentation allows the single instruction to encode multiple cores through the core identifier field while maintaining a clear, organized structure that is easier to manage than a monolithic instruction format, balancing functionality with structural simplicity
Data Source
AI summary
Methods and circuitry for processing a shadow scan instruction in a multi-threaded microprocessing environment include a bit sequence having a thread identifier, core identifiers and a shadow scan instruction. The core identifiers are assigned a state to identify microprocessor cores of a multi-core structure and are processed combinationally to determine if the shadow scan instruction is to be processed through a thread of the identified core. The processing of the shadow scan instruction through the thread of each of the identified cores is accomplished by a single load operation of the shadow scan instruction into the JTAG TAP controller.