Dedicated Shadow Stack Memory Protection With Lower WRSS Overhead
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory protection mechanisms, such as the CET mechanism, incur high performance overhead and are difficult to adjust for protecting sensitive data and code, leading to compatibility issues and inefficient memory access.
Innovation Solution
Implement a dedicated shadow stack page independent of the CET mechanism's shadow stack page, using WRSS instructions to write sensitive data and code, and apply overhead reduction techniques like lossless compression to minimize write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CET mechanism is used to protect sensitive data and code, then memory integrity is improved, but performance overhead increases and adaptability decreases
Solution Approach 1:
The patent divides memory into distinct regions: shadow stack pages for return addresses, code cache for executable code, and data regions. Each region has specific protection rules and access permissions. The shadow stack is further segmented into dedicated shadow stack pages that are independent from regular stack pages, allowing selective protection of critical memory areas without affecting overall system performance.
Solution Approach 2:
Different protection mechanisms are applied to different memory regions based on their specific requirements. Shadow stack pages use WRSS instructions for write protection, code cache uses execute-only permissions, and data regions use standard memory protection. This localized approach ensures that each region receives appropriate protection while minimizing performance overhead in non-critical areas.
2Reliability
If the CET mechanism is adjusted to protect sensitive data and code, then memory integrity is improved, but device complexity increases
Solution Approach 1:
The shadow stack mechanism, originally designed for return address protection, is extended to serve multiple functions: protecting return addresses, protecting sensitive data, and protecting sensitive code. The same WRSS instruction and shadow stack page structure are used across different protection scenarios, reducing the need for separate complex mechanisms and simplifying the overall system architecture.
3Reliability
If frequent memory access instructions are protected, then memory integrity is improved, but speed decreases
Solution Approach 1:
Instead of protecting all memory access instructions uniformly, the patent applies protection selectively to critical regions. Shadow stack pages protect only the specific memory locations where return addresses and sensitive data are stored. Code cache protects only executable code regions. This partial protection approach ensures integrity for critical operations while allowing fast access in non-critical areas, avoiding the performance penalty of universal protection.
Data Source
AI summary
A CET mechanism-based method for protecting the integrity of a general-purpose memory. In the method, the integrity of the general-purpose memory is protected on the basis of a CET mechanism. A dedicated shadow stack page is provided, and is independent of the shadow stack page maintained by the CET mechanism itself, and overhead reduction processing adaptive to content to be written that is written to the dedicated shadow stack page and requires writing overhead reduction is performed on the content to be written, so as to reduce the number of times of using WRSS instructions, such that the integrity of sensitive data and/or sensitive codes is protected in the case of using lower overhead, and performance overhead of a processor in the protection of the integrity of the general-purpose memory is reduced, thereby improving the efficiency of processing other tasks by the processor.