Shadow State Interpretation for Nested Virtual Processors
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Solution Overview
Problem
Existing virtualized computing environments lack hardware-assisted support for additional levels of virtualization beyond the first two levels, leading to performance issues and increased latency.
Innovation Solution
Implementing a computer program product that enables hardware-assisted interpretative execution for nested guests by providing accessibility to the context of a guest on one level through a shadow control structure, allowing the physical processor to perform actions on behalf of the virtual processor, thereby improving system performance and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional levels of virtualization are provided by software, then more nested guests can be supported, but system performance deteriorates and latency increases due to lack of hardware acceleration
Solution Approach 1:
The patent implements nested virtualization by allowing virtual processors to execute within virtualized environments that are themselves virtualized. The shadow control structure enables a first-level hypervisor to create and manage second-level hypervisors, which in turn can create third-level guests, forming a nested hierarchy where each level operates within the context of the previous level while maintaining hardware-assisted performance
Solution Approach 2:
The shadow control structure acts as an intermediary mechanism that bridges the gap between hardware virtualization capabilities and software-emulated virtualization levels. It provides the physical processor with controlled access to virtual processor state information, enabling hardware-assisted interpretation for nested guests without requiring full software emulation, thus maintaining performance while extending virtualization depth
2Adaptability or versatility
If additional levels of virtualization are provided by software, then more nested guests can be supported, but latency increases due to software processing overhead
Solution Approach 1:
The nested virtualization architecture allows multiple hypervisor levels to coexist with the shadow control structure enabling direct hardware-assisted interpretation for each level. This eliminates the need for software-mediated instruction translation at each nesting level, significantly reducing the time required for context switching and instruction execution across virtualization boundaries
Solution Approach 2:
The shadow control structure serves as a low-latency intermediary that provides the physical processor with direct access to critical virtual processor state information through shadow copies. This eliminates time-consuming software walks through original control structures, reducing latency for memory management, interrupt handling, and context switching operations in nested virtualized environments
3Productivity
If hardware-assisted support is provided for only two levels of guests, then system performance is maintained, but additional virtualization levels cannot be supported
Solution Approach 1:
The shadow control structure implements a universal mechanism that extends hardware-assisted virtualization support beyond the traditional two-level limitation. By maintaining shadow copies of control structures that can be accessed by the physical processor, it enables the same hardware virtualization facilities to serve multiple nested hypervisor levels, making the system capable of supporting arbitrary nesting depths while preserving performance characteristics
Solution Approach 2:
The patent enables nested hypervisor architectures where first-level hypervisors can create and manage second-level hypervisors, which themselves can create third-level guests. The shadow control structure provides the hardware support needed for this nested hierarchy, allowing each level to benefit from hardware-assisted interpretation while maintaining the ability to nest additional virtualization levels beyond the traditional two-level constraint
Data Source
AI summary
Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.