Shadow Tag Memory for Cache Coherency Probe Reduction
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Solution Overview
Problem
Conventional caching techniques in processing systems lead to excessive probe traffic due to the implementation of coherency protocols in exclusive caching, which can impact caching performance by requiring unnecessary communication between cache levels.
Innovation Solution
Implementing a shadow tag memory that maintains state information for cachelines across multiple cache levels, allowing the shared cache to filter probes and track coherency states with higher granularity, thereby reducing probe traffic and improving caching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency protocols are implemented in exclusive caching, then data coherency is ensured, but excessive probe traffic is generated
Solution Approach 1:
The patent segments the cache hierarchy into multiple levels (L1, L2, L3 caches) with distinct coherency management responsibilities. Each cache level maintains its own shadow tag memory, dividing the coherency enforcement task across multiple independent units rather than requiring centralized probe traffic for every access.
Solution Approach 2:
Shadow tag memory acts as an intermediary structure between the cache data and the coherency protocol. Instead of directly probing caches for coherency checks, the system uses shadow tags to track cache line states (Valid, Dirty, Shared, Exclusive), enabling coherency decisions to be made based on shadow tag information rather than generating excessive probe traffic.
2Object-generated harmful factors
If shadow tag memory is implemented, then probe traffic is reduced, but memory structure complexity increases
Solution Approach 1:
The patent implements shadow tag memory as a simplified copy of the main tag structure. Each shadow tag entry contains only the essential coherency state information (Valid, Dirty, Shared, Exclusive bits) rather than full tag data, creating a lightweight duplicate that enables coherency management without replicating the entire tag complexity.
Solution Approach 2:
The shadow tag memory is updated in advance alongside cache line operations. When a cache line is loaded, evicted, or modified, the corresponding shadow tag is updated simultaneously, preparing coherency information before actual cache operations occur. This preliminary tracking eliminates the need for reactive probe traffic during coherency checks.
3Productivity
If fine-grained coherency tracking is implemented, then caching performance is improved, but system complexity increases
Solution Approach 1:
The patent applies different coherency tracking granularity to different cache levels. L1 caches maintain fine-grained per-cache-line shadow tags for immediate coherency decisions, while L2 and L3 caches use aggregated shadow tag information. This local differentiation enables high-performance coherency management where needed without uniformly increasing complexity across the entire system.
Data Source
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AI summary
A processing system (100) includes a plurality of processor cores (111, 112, 113, 114) and a plurality of private caches (131, 132, 133, 134). Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache (140) shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory (142) including a plurality of entries (216), each entry storing state information (215) for a corresponding cacheline of the first set of cachelines of one of the private caches.