Accelerator Partition Shadow Tags for Interleaved Chiplet Caches
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Solution Overview
Problem
Existing graphics processing unit (GPU) and accelerator hardware architectures face inefficiencies in managing shadow tags for interleaved chiplet caches, requiring additional storage as the number of interleaved caches changes, which is not feasible without structural modifications.
Innovation Solution
An indexing scheme that repurposes address bits by incorporating source chiplet IDs into shadow tags, allowing efficient management of interleaved caches without increasing storage requirements, adaptable to different combinations of chiplet and cache configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional storage is allocated for shadow tags as the number of interleaved caches changes, then cache coherency management capability is improved, but hardware structural complexity and manufacturing feasibility deteriorate
Solution Approach 1:
The patent changes the parameter representation by encoding shadow tag information using combinations of existing address bits and source chiplet IDs rather than allocating dedicated storage bits. This allows the system to adapt to different numbers of interleaved caches by varying the encoding parameters without changing the physical storage structure.
Solution Approach 2:
The patent makes existing address bits serve multiple functions: they simultaneously represent memory address information and shadow tag identification information. By incorporating source chiplet IDs into the address bit patterns, the same hardware structure can manage varying numbers of interleaved caches without requiring additional dedicated storage resources.
2Reliability
If shadow tag storage is increased to manage interleaved caches, then cache coherency is improved, but manufacturing yield and cost-effectiveness worsen
Solution Approach 1:
The patent changes the parameter encoding to use existing address bits combined with source chiplet IDs to represent shadow tags. This parameter transformation allows comprehensive cache coherency management across interleaved caches while maintaining the original hardware bit width, avoiding additional manufacturing complexity and preserving manufacturing yield.
Solution Approach 2:
The patent creates a virtual shadow tag structure by encoding tag information in the address bits themselves rather than maintaining separate physical shadow tag storage. This copying approach embeds the necessary coherency information directly in the address translation process, ensuring reliability without additional hardware that would complicate manufacturing.
3Productivity
If address bits are repurposed to incorporate source chiplet IDs, then shadow tag management efficiency is improved, but address encoding complexity increases
Solution Approach 1:
The patent makes address bits universal by having them simultaneously encode memory address information and shadow tag identification through the incorporation of source chiplet IDs. This multi-functionality improves shadow tag management efficiency as the same bits serve dual purposes without requiring separate encoding logic or additional processing steps.
Data Source
AI summary
The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.