Shallow Access Line Profile for DRAM Disturb Reduction

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Solution Overview

Problem

DRAMs experience significant access line disturb due to voltage on active portions affecting inactive memory cells, leading to inefficiencies in memory operations.

Innovation Solution

The architecture is modified by reshaping the access line saddle profile, repositioning active chop mask areas, and changing fin shape and size to reduce the distance between passing and active access lines, using different materials for shallow trench isolation regions and forming shallower access lines to minimize disturb effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the access line structure uses a standard configuration with active and isolation portions, then the access line can provide voltages to memory cells during memory operations, but voltage on the active portion disturbs inactive memory cells coupled to the passing access line

Engineering Contradiction:
Improvememory cell isolationVSAvoidaccess line disturb
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The access line is divided into multiple segments with different depths. The passing access line portion is positioned at a shallower depth than the active access line portion, creating vertical segmentation that electrically isolates inactive memory cells from voltage disturbances on the passing access line during memory operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical depth dimension to solve the interference problem. By positioning access line portions at different depths (shallower vs. deeper), the patent creates three-dimensional separation that reduces capacitive coupling and voltage disturbance between passing and active access lines, thereby improving memory cell isolation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the distance between passing and active access lines is reduced to improve device density, then more memory cells can be packed in the same area, but voltage interference between active and inactive memory cells increases

Engineering Contradiction:
Improvememory device densityVSAvoidvoltage interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent resolves the density-interference tradeoff by utilizing the vertical depth dimension. The passing access line is positioned at a first depth while the active access line is positioned at a second depth, allowing horizontal proximity for high density while maintaining vertical separation for electrical isolation, thus reducing voltage interference

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Different portions of the access line structure have different local properties - the passing access line portion has a shallower depth profile while the active access line portion has a deeper depth profile. This local differentiation in depth positioning allows each portion to optimize its function while minimizing interference to neighboring cells

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9349737B2Passing access line structure in a memory device
Publication Date: 2016.05.24 MICRON TECHNOLOGY INC
  • US9349737B2 patent drawing
  • US9349737B2 patent drawing
  • US9349737B2 patent drawing

AI summary

A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.