Shallow Contact Structure With Interconnect Layer for Lower Aspect Ratio
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues related to shallow contacts and aspect ratios.
Innovation Solution
The semiconductor device design incorporates a substrate with a word line structure, impurity regions, bottom shallow contacts, a first interconnect layer, top shallow contacts, and deep contacts, where the first interconnect layer reduces the aspect ratio of the bottom shallow contacts, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to improve computing ability, then device density and computing power are improved, but manufacturing complexity and fabrication difficulty increase
Solution Approach 1:
The contact structure is segmented into multiple components: bottom shallow contacts, top shallow contacts, and deep contacts. This segmentation allows each contact type to be optimized independently for its specific function, with bottom shallow contacts having smaller widths for high density and deep contacts having larger widths for low resistance, thereby resolving the contradiction between device scaling and fabrication complexity
Solution Approach 2:
The patent introduces a vertical dimension to the contact structure by creating multi-level contacts at different depths (shallow contacts near the surface, deep contacts extending deeper into the substrate). This dimensional approach allows simultaneous optimization of horizontal density and vertical electrical performance without increasing overall fabrication complexity
2Length of moving object
If shallow contacts are used to reduce device dimensions, then device size is reduced, but aspect ratio increases making fabrication more difficult
Solution Approach 1:
The contact structure employs a nested configuration where top shallow contacts are positioned above bottom shallow contacts, which in turn are positioned above deep contacts. This nesting allows the structure to achieve compact horizontal dimensions while distributing the vertical depth across multiple contact levels, thereby reducing the aspect ratio of individual contacts and improving manufacturability
Solution Approach 2:
By transitioning from a single-level contact to a multi-level contact structure, the patent distributes the contact function across different vertical levels. This dimensional approach reduces the aspect ratio of each individual contact while maintaining the overall compact device footprint, resolving the contradiction between size reduction and manufacturing precision
3Productivity
If contact widths are reduced to improve device density, then device density is improved, but contact resistance increases
Solution Approach 1:
The patent applies different contact width characteristics to different contact levels: bottom shallow contacts have smaller widths optimized for high device density, while deep contacts have larger widths optimized for low contact resistance. This local differentiation allows each contact type to be optimized for its specific function, resolving the contradiction between density and resistance
Solution Approach 2:
The multi-level contact structure allows the system to achieve both high density and low resistance by distributing contact functions across different vertical levels. Shallow contacts provide dense interconnect routing while deep contacts provide low-resistance access to active regions, simultaneously satisfying both requirements that would be conflicting in a single-level contact structure
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a word line structure positioned in the substrate; a plurality of impurity regions positioned in the substrate and adjacent to the word line structure; a plurality of bottom shallow contacts positioned on the word line structure; a first interconnect layer positioned on the plurality of bottom shallow contacts; a plurality of top shallow contacts positioned on the first interconnect layer; and a plurality of deep contacts positioned on the plurality of impurity regions. Top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.