Shallow Erase Voltage for SSD Secure Erase Time Reduction
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Solution Overview
Problem
Conventional SSDs face challenges with slow secure erase times and endurance stress when performing secure erase operations, especially as the NAND media approaches end of life, due to the need for multiple erase commands across multiple decks and the high program/erase cycle count.
Innovation Solution
Implementing a shallow erase technology that sets the erase voltage to a weaker erase voltage, allowing for faster and less stressful secure erase operations by moving the erase verify voltage up, reducing the time required to reach the EDTC state and minimizing the program/erase cycle count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional secure erase commands are executed on each block of NAND media, then data is securely eliminated from the media, but the erase time becomes excessively long and endurance stress increases significantly
Solution Approach 1:
The patent changes the erase voltage parameter from the conventional high erase voltage to a shallow erase voltage that is sufficient to reach the EDTC state but lower than traditional erase voltages. This parameter change enables faster erase operations while maintaining security requirements, directly resolving the contradiction between secure data elimination and excessive erase time
Solution Approach 2:
The patent applies partial action by using a shallow erase voltage that performs only the necessary portion of the erase operation needed to reach the EDTC state, rather than applying full conventional erase voltage. This partial action achieves the required security level with significantly reduced time and stress
2Reliability
If multiple erase commands are executed across multiple decks to complete secure erase, then thorough erasure is achieved, but the program/erase cycle count increases and endurance stress worsens
Solution Approach 1:
The patent changes the erase voltage parameter to a shallow erase voltage that achieves the EDTC state with fewer program/erase cycles. This parameter modification reduces the cumulative endurance stress across multiple decks while maintaining complete erasure effectiveness, resolving the contradiction between erasure completeness and endurance strength
Solution Approach 2:
The patent uses a disposable shallow erase voltage approach that consumes minimal program/erase cycles from the NAND media's endurance budget. Each shallow erase operation consumes far fewer cycles than conventional erases, making the erase operation effectively 'cheap' in terms of media wear while achieving complete security
3Reliability
If high erase voltage is applied to ensure secure erasure, then data is completely eliminated, but the time to reach EDTC state and the endurance stress increase
Solution Approach 1:
The patent optimizes the erase voltage parameter by using a shallow erase voltage that is calibrated to reach the EDTC state efficiently. This parameter change eliminates the need for high voltage while achieving the same security outcome faster, directly resolving the contradiction between complete data elimination and time to reach EDTC state
Data Source
AI summary
An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.