Shallow Junction Formation via Pulsed Laser Annealing

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Solution Overview

Problem

The formation of shallow junctions in semiconductor substrates using ion implantation and laser annealing is often contaminated due to the diffusion of elements from the interface layer, particularly oxygen, which degrades the substrate lattice quality, especially in back-illuminated CMOS image sensors.

Innovation Solution

A method involving ion implantation to create a predetermined ion-implanted region, followed by pulsed laser annealing with controlled energy density and pulse duration to form layers with low contaminant concentrations, and subsequent removal of the contaminated layer through chemical-mechanical polishing or wet etching to create a shallow junction free from contaminants.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If melting laser annealing treatment is applied to activate and diffuse dopants, then dopant activation is improved, but contaminant diffusion from the interface layer increases

Engineering Contradiction:
Improvedopant activationVSAvoidcontaminant diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes the contaminated interface layer through chemical-mechanical polishing or wet etching after laser annealing, extracting the harmful oxygen-containing layer that formed during the annealing process, thereby separating the beneficial dopant activation from the harmful contaminant incorporation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent optimizes laser parameters (energy density, pulse duration, wavelength) to control the annealing process, using specific parameter ranges that achieve dopant activation while minimizing the formation and diffusion of oxygen contaminants from the interface layer

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If ion implantation is used to create shallow junctions, then junction depth control is improved, but interface layer contamination occurs

Engineering Contradiction:
Improvejunction depth controlVSAvoidinterface layer contamination
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent performs ion implantation first to establish the dopant profile at the desired shallow depth, then applies laser annealing to activate the dopants, separating the depth control function (ion implantation) from the activation function (laser annealing) to achieve both precision and activation

Inventive Principle:
Principle #10Preliminary action

3Object-affected harmful factors

If the interface layer is removed and a capping layer is deposited, then oxidation is reduced, but contaminant diffusion still occurs during laser annealing

Engineering Contradiction:
ImproveoxidationVSAvoidcontaminant diffusion
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent allows the interface layer to remain during ion implantation and laser annealing, converting the previously harmful oxygen-containing layer into a source of controlled oxygen that can be subsequently removed by chemical-mechanical polishing or wet etching, thereby transforming the contamination problem into a controllable process step

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces contaminant diffusion, maintaining high lattice quality and forming a shallow junction with low contaminant concentrations, enhancing the performance of back-illuminated CMOS image sensors by minimizing the incorporation of contaminants during the melting laser annealing treatment.

Implementation Method 1

irradiating said first face with a pulsed laser beam to melt said semiconductor substrate

Methodology Applied
Scientific EffectLaser heating: Laser

Implementation Method 2

melt said semiconductor substrate to at least the predetermined implantation depth

Methodology Applied
Scientific EffectMelting: Melting

Implementation Method 3

bombarding a surface of the semiconductor substrate with ions at low energy to limit the dopant penetration and create a shallow ion implanted region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 4

Melting laser annealing treatment induces extremely high surface temperatures on the substrate (more than 1400°C to melt silicon)

Methodology Applied
Scientific EffectLaser heating: Laser

Implementation Method 5

At such very high temperature, the interface layer is always molten and diffuses inside the molten substrate

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentEP3370251B1Method for forming a shallow junction in a semiconductor substrate
Publication Date: 2020.11.04 LASER SYST & SOLUTIONS OF EURO
  • EP3370251B1 patent drawingFigure 1A~1B
  • EP3370251B1 patent drawingFigure 2

AI summary

The method comprises the steps of: a) bombarding a first face (1 a) of the semiconductor substrate (1) with ions so as to implant ions into said semiconductor substrate and to form an ion implanted region (4) having a predetermined implantation depth; and b) irradiating said first face with a pulsed laser beam so as to melt said semiconductor substrate to at least the predetermined implantation depth; characterized in that said pulsed laser beam has an energy density and a pulse duration selected to form within said ion implanted region (4) a first layer (6) extending from the first face (1a) and including implanted ions and contaminants having diffused therein and a second layer extending from the first layer (6) deeper into the semiconductor substrate and including implanted ions and contaminants in an atomic concentration of contaminants lower than 1018 at/cm3 and in that it further comprises a step c) of removing at least said first layer (6) from the semiconductor substrate, said junction being formed at the interface between said second layer (7) and a subjacent non-molten part of the semiconductor substrate (1).