Shallow Sub-Surface Zener Diode for CMOS Integration
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Solution Overview
Problem
Integrating a stable and reliable Zener diode with low breakdown voltage and low sub-breakdown leakage current into a CMOS logic fabrication process without adding significant processing steps is challenging, as laterally oriented Zener diodes exhibit operational variations and higher leakage currents, while conventional vertical Zener diodes require additional process steps.
Innovation Solution
The development of Zener diodes with shallow, sub-surface latitudinal Zener junctions and longitudinal p-n junctions, utilizing existing logic process steps, and incorporating a silicide blocking structure to prevent junction shorting, with anode contacts located exterior to the Zener junction region to minimize additional processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If laterally oriented Zener diodes are used, then fabrication process simplicity is maintained, but operational stability deteriorates and leakage current increases
Solution Approach 1:
The patent inverts the conventional lateral orientation of Zener diodes by implementing a vertical orientation where the p-n junction extends from the surface into the substrate. This inversion resolves the contradiction by achieving both fabrication simplicity (using standard CMOS vertical processes) and operational stability (reducing leakage current and improving reliability) simultaneously.
Solution Approach 2:
The patent transitions from a two-dimensional lateral junction to a three-dimensional vertical junction that extends through the substrate depth. This dimensional change enables the diode to benefit from the stability of vertical junctions while maintaining compatibility with planar CMOS fabrication processes, thus resolving the contradiction between ease of manufacture and reliability.
2Reliability
If conventional vertical Zener diodes are used, then operational stability improves, but fabrication process complexity increases
Solution Approach 1:
The patent makes the vertical Zener diode structure universal by designing it to be fabricated using the same standard CMOS logic process steps that are already employed in the technology node. The vertical junction, contact regions, and isolation structures all integrate with existing transistor fabrication sequences, eliminating the need for additional specialized process steps and thereby reducing fabrication complexity while maintaining operational stability.
Solution Approach 2:
The patent enables the vertical Zener diode to be self-fabricated within the existing CMOS process flow without requiring external or additional process modules. The diode structures utilize the same implantation, oxidation, and deposition steps that define the logic device characteristics, allowing the Zener diodes to be produced as an integrated part of the standard process rather than as a separate addition.
3Object-generated harmful factors
If shallow sub-surface latitudinal Zener junctions are used, then leakage current reduces, but junction stability against shorting deteriorates
Solution Approach 1:
The patent introduces a silicide blocking structure as an intermediary element positioned over the shallow sub-surface Zener junction. This blocking layer prevents direct silicide formation that would cause junction shorting, thereby protecting the stability of the shallow junction while allowing it to maintain low leakage current characteristics. The intermediary structure resolves the contradiction by enabling the benefits of shallow junctions without their inherent vulnerability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of Zener diodes with low leakage and low breakdown voltage using minimal additional processing steps, maintaining process simplicity and cost-effectiveness while ensuring the stability of shallow p-n junctions.
Implementation Method 1
disclosed embodiments may include a silicide blocking structure overlying the Zener junction regions to prevent shorting of the shallow junctions during silicide processing steps
Implementation Method 2
Any substantial difference in electric potential applied across this depletion region produces an electric field having a magnitude that is sufficiently large to induce tunneling of electrons from the valence band of the p-type material to the conduction band of the n-type material
Data Source
AI summary
A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.