Shallow Trench Isolation Structure for Uniform FinFET Dielectric Conversion
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Solution Overview
Problem
The formation of shallow trench isolation (STI) regions in semiconductor devices, particularly in FinFETs, results in non-uniform conversion of dielectric layers due to varying fin densities, leading to uneven etching and electrical performance issues.
Innovation Solution
A method is employed to control the height and width of fins in different regions, ensuring uniform conversion of a first dielectric layer to a second dielectric layer by adjusting the anneal process parameters, thereby achieving uniform dielectric quality and composition across these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fins are formed with varying densities in different regions to increase integration density, then more components can be integrated into a given area, but non-uniform conversion of dielectric layers occurs leading to uneven etching and electrical performance issues
Solution Approach 1:
The patent applies local quality by forming raised base portions in specific regions between fin pairs where needed, rather than uniformly across the entire substrate. This localized structural modification compensates for varying fin densities in different regions, enabling uniform dielectric layer conversion and etching rates while maintaining high integration density through selective rather than universal structural changes
2Reliability
If a first dielectric layer is formed to fill recesses between fins, then isolation is achieved, but non-uniform conversion to a second dielectric layer occurs due to varying recess depths and widths
Solution Approach 1:
The patent applies preliminary action by forming raised base portions before depositing the first dielectric layer. This pre-formation of structural support elements ensures that subsequent dielectric layers convert uniformly during thermal processing, as the raised bases provide consistent geometric constraints that promote uniform conversion rates across all regions, thereby improving both isolation quality and conversion uniformity
3Ease of manufacture
If the conversion process is performed without adjusting for varying fin geometries, then processing is simplified, but non-uniform etching rates result causing electrical performance issues
Solution Approach 1:
The patent applies parameter changes by modifying the physical geometry of the substrate through raised base portions, rather than changing conversion process parameters like temperature or time. This structural parameter modification ensures uniform etching rates and electrical performance while keeping the conversion process itself simple and unchanged, thus maintaining ease of manufacture while improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise control over the thickness and depth uniformity of the converted dielectric layer, enhancing electrical performance and yield by maintaining consistent etch rates and reducing manufacturing defects.
Implementation Method 1
converting a first dielectric layer to a second dielectric layer
Data Source
AI summary
A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.