Shallow Trench RF Grounding for Transistor Parasitic Reduction
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Solution Overview
Problem
Typical RF power transistors face issues with RF losses, lower gain, and reduced high-frequency performance due to the inherent resistance and inductance of metalized via holes used for grounding the source of each cell, which also affect input RF signal combining and output RF power extraction.
Innovation Solution
The use of an electrically-conductive shallow trench and substrate for improved RF grounding of the transistor electrode, reducing parasitic inductance and resistance by bringing the RF ground closer to the active area, thereby enhancing the transistor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metalized via holes are used to ground the source of each cell to the grounded metallization layer on the bottom of the high resistivity substrate, then the source can be electrically connected to ground, but the inherent resistance and inductance of the via holes cause RF losses, lower gain, and reduced high-frequency performance
Solution Approach 1:
The patent transitions from vertical grounding (via holes through substrate) to lateral/shallow trench grounding within the epitaxial layers. This dimensional change allows the ground connection to be made much closer to the active area, reducing the length of the ground path and thereby minimizing parasitic inductance and resistance that cause RF losses.
Solution Approach 2:
The patent creates a localized ground connection through shallow trenches positioned directly beneath or adjacent to the source region. This local grounding approach eliminates the need for long via hole paths, concentrating the ground connection where it is most effective and reducing the harmful parasitic effects in the critical RF path.
2Reliability
If metalized via holes are used for grounding, then the source can be connected to ground, but the inductance of the via holes lowers the high frequency performance of the transistor
Solution Approach 1:
The patent changes the grounding geometry from deep vertical via holes to shallow lateral trenches within the epitaxial layers. This dimensional reconfiguration dramatically reduces the inductive path length, enabling effective grounding at high frequencies where via hole inductance would otherwise be prohibitive.
Solution Approach 2:
The shallow ground trenches are formed during the epitaxial growth process itself, before subsequent metallization and device assembly steps. This preliminary integration of the ground structure eliminates the need for separate via hole formation and plating steps, and ensures the ground path is optimized for high-frequency performance from the outset.
3Reliability
If metalized via holes are used to ground the source, then grounding is achieved, but the resistance of the via holes reduces the effectiveness of input RF signal combining and output RF power extraction
Solution Approach 1:
The patent implements grounding locally through shallow trenches positioned immediately beneath the source region, creating a low-resistance ground path right where the RF signals are combined. This local placement minimizes the resistance in the critical signal combining area, maximizing RF productivity and efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher gain, higher saturation point, improved 3rd-order intercept, and more efficient RF signal combining and extraction, while simplifying the manufacturing process by reducing the need for plated air bridges and via holes.
Implementation Method 1
an electrically-conductive shallow trench electrically connecting the first transistor electrode to the grounding metallization layer by way of the electrically-conductive substrate
Data Source
AI summary
Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3rd-order intercept, more efficient combining of the input RF signal, and more efficient extraction of the output RF signal. Additional benefits include reduced process complexity, such as, reduced need for plated air bridges, via holes formation and plating, front and back lithography alignment.