Shaped Metal Interconnect Lines for Sub-10 nm Pitch Scaling
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling metal line features to sub-10 nanometer nodes due to variability and limitations in lithographic processes, leading to issues with overlay tolerances, critical dimension control, and resistance in via openings.
Innovation Solution
Implementing variable etch rate atomic layer deposition (ALD) based layers to create a desirable cross-sectional profile for metal lines, using dielectric layers with different etch rates in wet clean chemistry, and applying pitch division techniques for patterning hardmasks to form BEOL interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used for metal line patterning, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-10 nanometer nodes due to overlay tolerance and critical dimension control issues
Solution Approach 1:
The patent applies pitch quartering methodology that divides the patterning process into multiple stages, creating mandrels and spacers in sequential steps to achieve sub-lithographic pitch metal lines. This segmentation enables precise critical dimension control by breaking down the single-step lithography into manageable fabrication stages including mandrel formation, spacer deposition, and selective etching
Solution Approach 2:
The patent implements preliminary patterning actions by forming mandrels and spacers before final metal line definition. These preliminary structures serve as templates that guide subsequent etching processes, ensuring precise overlay tolerance and critical dimension control are achieved before the actual metal deposition occurs
2Productivity
If metal line pitch is scaled down to increase density, then productivity is improved, but manufacturing precision deteriorates due to lithography resolution limitations
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring by forming spacer layers that extend vertically from mandrels. This dimensional transition enables pitch quartering where the final metal line pitch is one-quarter of the original lithographic pattern pitch, achieving high density while maintaining precision through vertical spacer thickness control rather than horizontal lithographic resolution
3Reliability
If via opening resistance is reduced to improve signal transmission, then electrical conductivity is improved, but manufacturing precision deteriorates due to variability in via formation processes
Solution Approach 1:
The patent employs atomic layer deposition (ALD) to precisely control via opening dimensions and metal line profiles by adjusting deposition parameters such as thickness, temperature, and precursor flow rates. This parameter control enables consistent via formation with reduced variability, achieving both low resistance through optimized via geometry and high manufacturing precision through repeatable process parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces metal line resistance, maintains edge placement error margins, and enables continued scaling of metal layer pitches beyond the resolution capabilities of current lithography equipment, improving contact surface area and reducing signal delay.
Implementation Method 1
variable etch rate atomic layer deposition (ALD) based layers
Implementation Method 2
using dielectric layers with different etch rates in wet clean chemistry
Data Source
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AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.