Shaped Source/Drain Epitaxial Layers for FinFET Yield
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Solution Overview
Problem
In advanced semiconductor technology nodes, the epi source or drain structure in Fin FETs poses challenges for fin pitch scaling due to high source/drain sheet resistance and contact resistivity, which can negatively impact yield, especially in high-density devices like SRAM chips, where large epitaxial source/drain volumes are beneficial for performance but detrimental to yield.
Innovation Solution
The solution involves forming source/drain epitaxial structures with enhanced (100) crystallographic facet growth rates using high-temperature deposition processes or modified etch techniques, which promote preferred crystallographic orientations and reduce lateral growth, thereby minimizing contact resistance and preventing irregularities that can cause device failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large epitaxial source/drain volume is used to reduce sheet resistance and contact resistivity, then device performance is improved, but yield deteriorates in high-density devices due to fin pitch scaling limitations
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the epitaxial growth from conventional directions to the (100) facet, which fundamentally alters the growth characteristics. This parameter change enables lateral expansion of the source/drain volume while maintaining compatibility with scaled fin pitches, thus improving device performance without sacrificing yield in high-density configurations
Solution Approach 2:
The patent exploits the unique growth properties of the (100) crystallographic facet to achieve lateral expansion in the plane parallel to the fin surface. This dimensional approach allows the epitaxial structure to expand horizontally rather than only vertically, increasing the effective source/drain volume and contact area without increasing the vertical fin pitch, thereby resolving the contradiction between performance and yield
2Object-affected harmful factors
If epitaxial growth is used to increase source/drain volume for lower resistance, then contact resistivity is reduced, but fin pitch scaling is hindered due to lateral growth irregularities
Solution Approach 1:
By changing the crystallographic facet parameter to (100), the patent transforms the growth behavior from isotropic or conventionally anisotropic growth to a directionally controlled process. This enables predictable lateral expansion that can be precisely managed during fin pitch scaling, reducing contact resistivity without creating the irregularities that would otherwise constrain fin pitch reduction
3Productivity
If conventional epitaxial growth is used to form source/drain structures, then device area is reduced for higher density, but source/drain sheet resistance increases
Solution Approach 1:
The patent utilizes the (100) facet's inherent growth preference to expand the source/drain structure laterally in the plane of the fin surface. This lateral expansion increases the effective conduction path width and contact area without increasing the vertical dimension, thereby reducing sheet resistance while maintaining the compact footprint required for high device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance by reducing source/drain resistance and preventing unwanted contacts, enhancing the yield and reliability of high-density integrated circuits such as SRAMs by controlling epitaxial growth and shaping the epitaxial structures to prevent leakage and short circuits.
Implementation Method 1
a source/drain epitaxial structure is formed in the trench using an epitaxial process
Implementation Method 2
The selective removal process removes exposed portions of the source/drain epitaxial structure and the dielectric layer, and exposes a top surface of the fin structure
Data Source
AI summary
In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.