Share Lock Counter Management for Multi-Core Storage Arrays

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Solution Overview

Problem

Conventional mutexes for multi-core storage processors cause 'cache trashing' when releasing share locks, leading to inefficiency due to invalidation of cache regions as share lock counters are decremented by incorrect CPU cores.

Innovation Solution

The improved technique manages resources by decrementing share lock counters associated with the CPU cores that release the share locks, rather than the cores that acquired them, ensuring each CPU core updates its own counter, thus avoiding cache trashing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional mutexes decrement share lock counters of the original acquiring CPU cores, then accurate tracking of share locks is maintained, but cache trashing occurs and system efficiency deteriorates

Engineering Contradiction:

Improveshare lock counter accuracyVSAvoidsystem efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent inverts the conventional approach by having the releasing CPU core decrement its own mutex sub-object's share lock counter instead of decrementing the counter of the original acquiring core. This inversion eliminates cache trashing because each core only modifies its own cached data, while still maintaining accurate tracking of share lock states through the cumulative counter values.

Inventive Principle:

Principle #13The other way round (Inversion)

2Loss of information

If share lock counters are updated in per-core mutex sub-objects, then precise per-core tracking is achieved, but cache invalidation propagates across cores causing performance degradation

Engineering Contradiction:

Improveshare lock state trackingVSAvoidcache invalidation time

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

The patent applies local quality by allowing each CPU core to independently manage and modify only its own mutex sub-object's share lock counter in its local cache. This localized modification approach eliminates the need for widespread cache invalidation across all cores, as each core's cache changes are independent and do not require synchronization with other cores' caches.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If mutex sub-objects are instantiated for each CPU core, then parallel access management is enabled, but cache coherence issues arise when cores modify different sub-objects

Engineering Contradiction:

Improvemulti-core parallel accessVSAvoidcache coherence

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent segments the mutex management into separate mutex sub-objects for each CPU core, where each sub-object contains a share lock counter specific to that core. This segmentation allows each core to independently modify its own sub-object without affecting the cache coherence of other cores' sub-objects, enabling parallel access while maintaining cache stability.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9201802B1Managing read/write locks for multiple CPU cores for efficient access to storage array resources

Publication Date: 2015.12.01 EMC IP HLDG CO LLC

AI summary

A technique for managing resources on a storage array having multiple CPU cores releases share locks on a resource by decrementing share lock counters associated with the CPU cores that release the share locks, regardless of whether these are the same as the CPU cores that acquired the share locks. As each CPU core changes its own share lock counter, cache trashing caused by changing share lock counters associated with other CPU cores can be avoided.