Shareable ECC Cell Array for DRAM Parity Storage
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Solution Overview
Problem
As semiconductor memory devices, such as DRAM, face increased bit error rates due to decreasing capacitance values and current leakage, leading to deteriorated data reliability, existing technologies require separate memory regions for storing internal and external parity bits for error correction, resulting in significant chip size overhead.
Innovation Solution
A memory device with a shareable ECC cell array that uses an ECC engine to generate internal parity bits and an ECC select unit to store either internal or external parity bits based on control signals, allowing both to be stored in a single memory cell array, reducing chip size overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory regions are used to store internal and external parity bits, then data reliability is improved through error correction, but chip size overhead increases significantly
Solution Approach 1:
The patent merges the storage of internal parity bits and external parity bits into a single shared ECC cell array. The ECC select unit determines which parity bits are stored based on operation mode: during write operations, external parity bits from the memory controller are stored; during read operations, internally generated parity bits are stored. This sharing approach maintains error correction capability while significantly reducing the memory area required compared to separate storage regions.
Solution Approach 2:
The patent introduces a dynamic selection mechanism through the ECC select unit that switches between storing external parity bits during write operations and internal parity bits during read operations based on control signals. This dynamic approach allows the same storage resource to serve different functions at different times, optimizing the balance between reliability and chip area utilization.
2Reliability
If internal parity bits are generated by the ECC engine, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent makes the ECC cell array multi-functional by enabling it to store both external parity bits during write operations and internal parity bits during read operations. The ECC select unit acts as a controller that directs the storage of appropriate parity bits based on the current operation mode, allowing a single structure to fulfill multiple roles without proportionally increasing device complexity.
Solution Approach 2:
The ECC select unit serves as an intermediary component that manages the complexity of parity bit selection and storage. It receives control signals, determines whether to store external or internal parity bits, and coordinates the appropriate data path. This intermediary structure simplifies the overall system by providing a clear decision-making mechanism for parity bit handling.
3Area of stationary object
If a shareable ECC cell array is used, then chip size overhead is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the ECC cell array into different functional states through the ECC select unit, which separates the storage of external parity bits during write operations from the storage of internal parity bits during read operations. This segmentation allows the same physical array to be used for different purposes at different times, reducing the need for separate dedicated storage regions and thereby reducing chip area requirements.
Data Source
AI summary
A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.