Shared Access Transistors for Resistive Memory Scaling
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Solution Overview
Problem
Resistive nonvolatile memory cells require a large current for switching, which limits the scalability of memory cell arrays due to the need for larger access transistors, making it difficult to reduce chip area and height.
Innovation Solution
The use of shared access transistors and write assist transistors across multiple resistive storage elements allows for increased write current without increasing transistor size, enabling reduced transistor footprints and improved device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated access transistors are used for each resistive memory cell, then reliable write operations can be performed, but the transistor size must be large to provide sufficient write current
Solution Approach 1:
The patent merges the write current provision function from dedicated access transistors to shared write assist transistors. Multiple memory cells share common write assist transistors that provide the necessary write current through shared bit lines, eliminating the need for each cell to have its own large access transistor dedicated to write operations.
Solution Approach 2:
The write assist transistors serve multiple functions: they provide write current to multiple different memory cells through shared bit lines, and can be selectively activated based on which cell needs writing. This multi-functional approach replaces the single-function dedicated access transistor per cell.
2Reliability
If larger access transistors are used to provide sufficient write current, then write operations remain reliable, but device density decreases
Solution Approach 1:
The patent combines the write current provision capability from multiple access transistors into shared write assist transistors. By merging this function at the transistor level, the patent achieves reliable write operations while using fewer, smaller transistors, thereby increasing device density.
Solution Approach 2:
The patent introduces a new dimensional approach by using shared bit lines as an additional current path dimension. Instead of relying solely on the width of individual access transistors, the write current can flow through multiple cells in parallel via shared bit lines, effectively increasing current capacity without increasing individual transistor size.
3Area of stationary object
If memory cell arrays are scaled down to reduce chip area, then chip footprint decreases, but write current requirements become harder to meet with smaller transistors
Solution Approach 1:
The write assist transistors are designed to serve multiple memory cells universally through shared bit lines. This multi-functional design allows the same transistor to provide write current to different cells at different times, maintaining adequate write current capability even as individual cell sizes and associated transistor sizes are reduced for scaling.
Solution Approach 2:
The patent uses shared bit lines to create an additional current delivery dimension. When scaling down, instead of reducing write current capability, the system compensates by enabling current to flow through multiple cells in parallel via the shared bit line dimension, maintaining power capability despite smaller individual components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases device density by reducing the physical size of access transistors while maintaining effective write operations, addressing the scalability challenges of resistive memory cell arrays.
Implementation Method 1
a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node
Implementation Method 2
A resistive memory cell may store information by changing the electrical resistance of a non-volatile memory device
Implementation Method 3
Spin transfer torque (STT) or spin transfer switching, uses spin-aligned ('polarized') electrons to directly apply a torque on the MTJ layers
Data Source
AI summary
A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.