Shared ADC Circuitry for Column Parallel Image Sensors
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Solution Overview
Problem
Conventional image sensors with column parallel readout architecture require a significant number of analog-to-digital converters (ADCs) per column, leading to high power consumption and increased physical size, making it challenging to manufacture small image sensors while maintaining fast readout performance.
Innovation Solution
Implementing a shared ADC circuit architecture where multiple adjacent columns in an image sensor pixel array share a single ADC circuit, allowing simultaneous sampling and conversion of image signals from multiple columns, thereby reducing the number of ADCs required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If one ADC circuit is provided per column in column parallel readout architecture, then readout speed is improved, but power consumption and physical size increase substantially
Solution Approach 1:
The patent merges multiple ADC circuits into a single shared ADC circuit that serves multiple columns. The shared ADC circuit includes a sample holder with multiple sampling capacitors (one per column) and a single conversion unit that sequentially converts signals from all columns. This consolidation maintains parallel readout capability while dramatically reducing the number of ADC circuits from N (one per column) to 1, thereby reducing power consumption and physical footprint.
Solution Approach 2:
The patent segments the ADC functionality into two distinct parts: (1) parallel sampling stage with individual sampling capacitors for each column that operate simultaneously, and (2) sequential conversion stage with a single ADC that converts signals one at a time. This segmentation allows the system to benefit from parallel sampling (maintaining speed) while using sequential conversion (reducing power and size), effectively resolving the contradiction between readout speed and power consumption.
2Speed
If one ADC circuit is provided per column in column parallel readout architecture, then readout speed is improved, but die size increases
Solution Approach 1:
The patent merges multiple ADC circuits into a single shared ADC circuit that serves multiple columns. The shared ADC circuit includes a sample holder with multiple sampling capacitors (one per column) and a single conversion unit that sequentially converts signals from all columns. This consolidation maintains parallel readout capability while dramatically reducing the number of ADC circuits from N (one per column) to 1, thereby reducing power consumption and physical footprint.
Solution Approach 2:
The patent transitions from a spatial distribution of ADC circuits (one per column in parallel) to a temporal distribution (single ADC serving all columns sequentially). By moving the conversion function to the time domain rather than maintaining it in the spatial domain, the patent reduces the physical area required while preserving the parallel sampling capability in the spatial domain.
3Device complexity
If serial readout is used with a single ADC circuit per column, then device complexity is reduced, but readout time increases significantly
Solution Approach 1:
The patent segments the readout process into two distinct phases: (1) parallel sampling phase where all columns sample simultaneously using individual sampling capacitors, and (2) sequential conversion phase where a single ADC converts signals one at a time. This segmentation allows the system to benefit from parallel sampling (maintaining speed) while using sequential conversion (reducing power and size), effectively resolving the contradiction between readout speed and power consumption.
Solution Approach 2:
The patent performs preliminary parallel sampling of all column signals before conversion. The sample holder with multiple sampling capacitors captures all column signals simultaneously in advance, so that when the single ADC begins sequential conversion, all signals are already ready and waiting. This preliminary parallel action eliminates the waiting time that would otherwise occur in purely serial systems, significantly reducing total readout time.
Data Source
AI summary
Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.