Shared ADC Sequencer for Priority Conversion Queue Timing
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Solution Overview
Problem
In embedded system on a chip (SoC) solutions, the sharing of analog-to-digital converter (ADC) resources across multiple hardware and software conversion demands poses challenges in meeting system timing without degrading responsiveness, particularly in time-critical applications like networked motion control/drives that require minimal packet jitter and latencies.
Innovation Solution
The ADC subsystem employs a sequencer with programmable step configuration registers and multiplexers to manage ADC conversion queues, allowing for hardware and software synchronization, preemption, and flexible trigger configurations, ensuring efficient sharing of ADC resources while maintaining high timing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ADC resources are shared across multiple hardware and software conversion demands, then resource utilization is improved, but system timing precision and responsiveness deteriorate
Solution Approach 1:
The patent segments the ADC resource sharing mechanism into multiple independent conversion queues (hardware queue and software queue) with distinct priority levels. The sequencer is divided into multiple state machines that independently manage different queues, allowing simultaneous processing of multiple conversion demands without mutual interference, thus maintaining timing precision while enabling resource sharing.
Solution Approach 2:
The patent introduces a priority arbitration mechanism as an intermediary between multiple conversion demands and the ADC resource. This arbitrator dynamically selects which queue receives ADC service based on priority levels and timing requirements, mediating access to the shared resource and ensuring that time-critical conversions receive appropriate precedence, thereby maintaining timing precision under shared resource conditions.
2Loss of time
If ADC conversion queues are processed sequentially, then timing precision is improved, but system responsiveness and throughput deteriorate
Solution Approach 1:
The patent implements dynamic queue management where the processing order and priority of conversion queues can change based on real-time conditions. The sequencer state machines can dynamically switch between servicing hardware queues and software queues based on timing requirements, conversion completion status, and system priorities, allowing the system to adaptively balance timing precision and throughput rather than following a fixed sequential pattern.
Solution Approach 2:
The patent ensures continuous ADC utilization by implementing overlapping conversion operations across multiple queues. While one queue is being serviced, the sequencer prepares the next conversion request in another queue, eliminating idle periods and ensuring the ADC resource is continuously productive. This continuous operation maintains high throughput while timing precision is preserved through priority-based scheduling.
3Loss of time
If hardware synchronization is implemented for time-critical conversions, then timing precision is improved, but system complexity and software flexibility deteriorate
Solution Approach 1:
The patent designs the sequencer state machines to perform multiple functions: they can service hardware-triggered conversions, software-initiated conversions, and priority-arbitrated requests using the same basic processing framework. This universal approach allows time-critical hardware synchronization to be implemented without creating separate complex processing paths, as the same sequencer infrastructure handles all conversion types with appropriate priority weighting.
Data Source
AI summary
An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions.