Shared ADC Architecture for TX Observation in Time-Interleaved Receivers
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Solution Overview
Problem
Existing ADC architectures face challenges in achieving efficient and compact implementation for observing TX signals, requiring significant circuit-level overhead for calibration and operation, which is not addressed by existing solutions like time-interleaved ADCs or digital predistortion methods.
Innovation Solution
An ADC system that reuses the existing infrastructure of time-interleaved ADC circuits for both RX and TX observation by sharing common clock, reference voltage, bias, and calibration circuitry, allowing the TX observation ADC to be compact in terms of chip area and power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated TX observation ADC is implemented with full calibration infrastructure, then measurement precision is improved, but device complexity increases significantly
Solution Approach 1:
The patent applies universality by enabling the RX ADC infrastructure to serve dual purposes: its original RX signal conversion function and an additional TX observation function. The same ADC circuits, clock interfaces, reference voltage generators, and calibration systems are reused for both RX and TX observations, eliminating the need for a separate dedicated TX observation ADC and its associated overhead infrastructure.
Solution Approach 2:
The patent uses copying by creating a virtual copy of the RX ADC observation capability for TX signal monitoring. Instead of building a complete physical duplicate of the ADC system, the invention leverages the existing RX ADC circuit design and replicates its observation functionality through digital signal processing and feedback path routing, thereby reducing hardware complexity while maintaining measurement precision.
2Productivity
If time-interleaved ADC architecture is used to combine low-speed high-resolution and high-speed low-resolution ADCs, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple ADC circuits into a unified time-interleaved architecture where low-speed high-resolution ADCs and high-speed low-resolution ADCs work together as an integrated system. The merging is achieved through shared clock interfaces, combined digital output processing, and coordinated calibration procedures, improving overall signal observation efficiency while managing complexity through systematic integration rather than separate independent circuits.
3Measurement precision
If multiple ADC circuits are implemented for RX and TX observation, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent reduces power dissipation by making the ADC circuits universal - the same physical ADC infrastructure performs both RX signal conversion and TX signal observation. This multi-functionality eliminates redundant power consumption that would occur if separate ADC circuits were dedicated exclusively to RX and TX functions, as calibration systems, reference voltages, and digital processing resources are shared between both observation paths.
Data Source
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AI summary
An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.