Shared Adder Circuit for Binary Parallel Arithmetic

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Solution Overview

Problem

Semiconductor memory devices face challenges in achieving high data reliability, fast memory access, low power consumption, and reduced chip size due to the space and power requirements of arithmetic circuitry for performing operations.

Innovation Solution

The integration of an arithmetic logic unit (ALU) with shared adder circuitry capable of performing both binary addition and multiplication operations, reducing the need for separate logic circuitry and thereby minimizing space and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate arithmetic circuitry is implemented for addition and multiplication operations, then operational capability is improved, but chip area and power consumption increase

Engineering Contradiction:
Improvearithmetic operational capabilityVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent combines separate adder and multiplier circuits into a unified shared adder circuit that performs both addition and multiplication operations. The circuit shares common components including carry propagate generators, sum generators, and control logic, thereby reducing the overall chip area while maintaining full arithmetic functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared adder circuit is designed with multi-functionality to handle both addition and multiplication operations. Control signals dynamically configure the circuit to perform different operations based on operational mode, allowing a single circuit structure to replace multiple dedicated circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate arithmetic circuitry is implemented for addition and multiplication operations, then operational capability is improved, but power consumption increases

Engineering Contradiction:
Improvearithmetic operational capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent combines separate adder and multiplier circuits into a unified shared adder circuit that performs both addition and multiplication operations. The circuit shares common components including carry propagate generators, sum generators, and control logic, thereby reducing the overall chip area while maintaining full arithmetic functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared adder circuit is designed with multi-functionality to handle both addition and multiplication operations. Control signals dynamically configure the circuit to perform different operations based on operational mode, allowing a single circuit structure to replace multiple dedicated circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If arithmetic operations are performed using external ALU, then computational function is improved, but memory access speed and reliability are compromised

Engineering Contradiction:
Improvecomputational functionVSAvoidmemory access speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces a shared adder circuit as an intermediary component that enables arithmetic operations within the memory device itself, eliminating the need for external ALU accesses. This intermediary circuit facilitates fast on-chip computation while maintaining the memory's primary storage function.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Adaptability or versatility

If arithmetic operations are performed using external ALU, then computational function is improved, but data reliability is compromised

Engineering Contradiction:
Improvecomputational functionVSAvoiddata reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a shared adder circuit as an intermediary component that enables arithmetic operations within the memory device itself, eliminating the need for external ALU accesses. This intermediary circuit facilitates fast on-chip computation while maintaining the memory's primary storage function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11740871B2Binary parallel adder and multiplier
Publication Date: 2023.08.29 MICRON TECHNOLOGY INC
  • US11740871B2 patent drawing
  • US11740871B2 patent drawing
  • US11740871B2 patent drawing

AI summary

An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.