Shared-Adder Digital Filter Circuit for Crosstalk Compensation
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Solution Overview
Problem
Existing digital filter circuits face challenges in processing high-data-rate and high-parallelism digital signals efficiently due to increased complexity and cost associated with crosstalk compensation, which becomes more pronounced with higher numbers of channels or polyphases.
Innovation Solution
A digital filter circuit with a modified architecture that includes a pre-adder circuit, convolution circuit, and post-adder circuit, where the number of convolution sub-circuits exceeds the pre-adder and post-adder sub-circuits, allowing for shared pre- and post-processing tasks, reducing the number of adder and multiplier sub-circuits, and enabling a resource-efficient design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional digital filter circuits are used to process high-data-rate signals with multiple channels, then signal processing capability is improved, but hardware complexity and cost increase quadratically with the number of channels
Solution Approach 1:
The patent combines multiple adder sub-circuits into a shared resource that is time-multiplexed across different channels. Instead of having dedicated adders for each channel combination, a single adder unit is shared among multiple channels through temporal division, reducing the total number of adder sub-circuits from O(N²) to O(N) where N is the number of channels.
Solution Approach 2:
The patent introduces dynamic control mechanisms including enable signals and selection logic that allow the adder sub-circuits to be selectively activated based on the current processing requirements. This dynamic activation pattern enables the same hardware resources to serve multiple functions across different time periods and channel combinations.
2Reliability
If the number of adder and multiplier sub-circuits is increased to maintain effective crosstalk compensation, then filtering performance is improved, but hardware resource consumption increases
Solution Approach 1:
The patent implements periodic activation of adder sub-circuits where each adder is enabled in alternating time periods rather than continuously. This periodic action allows the same adder resource to service multiple channel pairs at different time intervals, maintaining crosstalk compensation effectiveness while reducing the total number of adder sub-circuits required.
Solution Approach 2:
The patent designs adder sub-circuits to serve multiple functions across different channel combinations. A single adder sub-circuit can process data from different channel pairs at different time periods, making the hardware resource universal rather than dedicated to a single function or channel pair.
Data Source
AI summary
A digital filter circuit is described. The digital filter circuit includes a pre-adder circuit, a convolution circuit, and a post-adder circuit. The pre-adder circuit includes a number of n pre-adder sub-circuits, wherein n is an integer greater than or equal to 2. The convolution circuit includes a number of m convolution sub-circuits, wherein m is an integer. The post-adder circuit includes a number of k post-adder sub-circuits, wherein k is an integer greater than or equal to 2. The number m of convolution sub-circuits is greater than the number n of pre-adder sub-circuits of the pre-adder circuit. The number m of convolution sub-circuits is greater than the number k of post-adder sub-circuits of the post-adder circuit. Further, an electronic device is described.